s32k144w_pac/pdb0/
chdly7.rs

1#[doc = "Register `CH%sDLY7` reader"]
2pub struct R(crate::R<CHDLY7_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CHDLY7_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CHDLY7_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CHDLY7_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH%sDLY7` writer"]
17pub struct W(crate::W<CHDLY7_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CHDLY7_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CHDLY7_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CHDLY7_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DLY` reader - PDB Channel Delay"]
38pub struct DLY_R(crate::FieldReader<u16, u16>);
39impl DLY_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u16) -> Self {
42        DLY_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for DLY_R {
46    type Target = crate::FieldReader<u16, u16>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `DLY` writer - PDB Channel Delay"]
53pub struct DLY_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> DLY_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u16) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
61        self.w
62    }
63}
64impl R {
65    #[doc = "Bits 0:15 - PDB Channel Delay"]
66    #[inline(always)]
67    pub fn dly(&self) -> DLY_R {
68        DLY_R::new((self.bits & 0xffff) as u16)
69    }
70}
71impl W {
72    #[doc = "Bits 0:15 - PDB Channel Delay"]
73    #[inline(always)]
74    pub fn dly(&mut self) -> DLY_W {
75        DLY_W { w: self }
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "Channel n Delay 7 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chdly7](index.html) module"]
85pub struct CHDLY7_SPEC;
86impl crate::RegisterSpec for CHDLY7_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [chdly7::R](R) reader structure"]
90impl crate::Readable for CHDLY7_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [chdly7::W](W) writer structure"]
94impl crate::Writable for CHDLY7_SPEC {
95    type Writer = W;
96}
97#[doc = "`reset()` method sets CH%sDLY7 to value 0"]
98impl crate::Resettable for CHDLY7_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
s32k144w_pac/pdb0/chdly7.rs

s32k144w_pac/pdb0/
chdly7.rs
