s32k144w_pac/dma/
tcd6_csr.rs

1#[doc = "Register `TCD6_CSR` reader"]
2pub struct R(crate::R<TCD6_CSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TCD6_CSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TCD6_CSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TCD6_CSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TCD6_CSR` writer"]
17pub struct W(crate::W<TCD6_CSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TCD6_CSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TCD6_CSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TCD6_CSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Channel Start\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum START_A {
40    #[doc = "0: The channel is not explicitly started."]
41    START_0 = 0,
42    #[doc = "1: The channel is explicitly started via a software initiated service request."]
43    START_1 = 1,
44}
45impl From<START_A> for bool {
46    #[inline(always)]
47    fn from(variant: START_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `START` reader - Channel Start"]
52pub struct START_R(crate::FieldReader<bool, START_A>);
53impl START_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        START_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> START_A {
61        match self.bits {
62            false => START_A::START_0,
63            true => START_A::START_1,
64        }
65    }
66    #[doc = "Checks if the value of the field is `START_0`"]
67    #[inline(always)]
68    pub fn is_start_0(&self) -> bool {
69        **self == START_A::START_0
70    }
71    #[doc = "Checks if the value of the field is `START_1`"]
72    #[inline(always)]
73    pub fn is_start_1(&self) -> bool {
74        **self == START_A::START_1
75    }
76}
77impl core::ops::Deref for START_R {
78    type Target = crate::FieldReader<bool, START_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `START` writer - Channel Start"]
85pub struct START_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> START_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: START_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "The channel is not explicitly started."]
95    #[inline(always)]
96    pub fn start_0(self) -> &'a mut W {
97        self.variant(START_A::START_0)
98    }
99    #[doc = "The channel is explicitly started via a software initiated service request."]
100    #[inline(always)]
101    pub fn start_1(self) -> &'a mut W {
102        self.variant(START_A::START_1)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01);
118        self.w
119    }
120}
121#[doc = "Enable an interrupt when major iteration count completes.\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123pub enum INTMAJOR_A {
124    #[doc = "0: The end-of-major loop interrupt is disabled."]
125    INTMAJOR_0 = 0,
126    #[doc = "1: The end-of-major loop interrupt is enabled."]
127    INTMAJOR_1 = 1,
128}
129impl From<INTMAJOR_A> for bool {
130    #[inline(always)]
131    fn from(variant: INTMAJOR_A) -> Self {
132        variant as u8 != 0
133    }
134}
135#[doc = "Field `INTMAJOR` reader - Enable an interrupt when major iteration count completes."]
136pub struct INTMAJOR_R(crate::FieldReader<bool, INTMAJOR_A>);
137impl INTMAJOR_R {
138    #[inline(always)]
139    pub(crate) fn new(bits: bool) -> Self {
140        INTMAJOR_R(crate::FieldReader::new(bits))
141    }
142    #[doc = r"Get enumerated values variant"]
143    #[inline(always)]
144    pub fn variant(&self) -> INTMAJOR_A {
145        match self.bits {
146            false => INTMAJOR_A::INTMAJOR_0,
147            true => INTMAJOR_A::INTMAJOR_1,
148        }
149    }
150    #[doc = "Checks if the value of the field is `INTMAJOR_0`"]
151    #[inline(always)]
152    pub fn is_intmajor_0(&self) -> bool {
153        **self == INTMAJOR_A::INTMAJOR_0
154    }
155    #[doc = "Checks if the value of the field is `INTMAJOR_1`"]
156    #[inline(always)]
157    pub fn is_intmajor_1(&self) -> bool {
158        **self == INTMAJOR_A::INTMAJOR_1
159    }
160}
161impl core::ops::Deref for INTMAJOR_R {
162    type Target = crate::FieldReader<bool, INTMAJOR_A>;
163    #[inline(always)]
164    fn deref(&self) -> &Self::Target {
165        &self.0
166    }
167}
168#[doc = "Field `INTMAJOR` writer - Enable an interrupt when major iteration count completes."]
169pub struct INTMAJOR_W<'a> {
170    w: &'a mut W,
171}
172impl<'a> INTMAJOR_W<'a> {
173    #[doc = r"Writes `variant` to the field"]
174    #[inline(always)]
175    pub fn variant(self, variant: INTMAJOR_A) -> &'a mut W {
176        self.bit(variant.into())
177    }
178    #[doc = "The end-of-major loop interrupt is disabled."]
179    #[inline(always)]
180    pub fn intmajor_0(self) -> &'a mut W {
181        self.variant(INTMAJOR_A::INTMAJOR_0)
182    }
183    #[doc = "The end-of-major loop interrupt is enabled."]
184    #[inline(always)]
185    pub fn intmajor_1(self) -> &'a mut W {
186        self.variant(INTMAJOR_A::INTMAJOR_1)
187    }
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1);
202        self.w
203    }
204}
205#[doc = "Enable an interrupt when major counter is half complete.\n\nValue on reset: 0"]
206#[derive(Clone, Copy, Debug, PartialEq)]
207pub enum INTHALF_A {
208    #[doc = "0: The half-point interrupt is disabled."]
209    INTHALF_0 = 0,
210    #[doc = "1: The half-point interrupt is enabled."]
211    INTHALF_1 = 1,
212}
213impl From<INTHALF_A> for bool {
214    #[inline(always)]
215    fn from(variant: INTHALF_A) -> Self {
216        variant as u8 != 0
217    }
218}
219#[doc = "Field `INTHALF` reader - Enable an interrupt when major counter is half complete."]
220pub struct INTHALF_R(crate::FieldReader<bool, INTHALF_A>);
221impl INTHALF_R {
222    #[inline(always)]
223    pub(crate) fn new(bits: bool) -> Self {
224        INTHALF_R(crate::FieldReader::new(bits))
225    }
226    #[doc = r"Get enumerated values variant"]
227    #[inline(always)]
228    pub fn variant(&self) -> INTHALF_A {
229        match self.bits {
230            false => INTHALF_A::INTHALF_0,
231            true => INTHALF_A::INTHALF_1,
232        }
233    }
234    #[doc = "Checks if the value of the field is `INTHALF_0`"]
235    #[inline(always)]
236    pub fn is_inthalf_0(&self) -> bool {
237        **self == INTHALF_A::INTHALF_0
238    }
239    #[doc = "Checks if the value of the field is `INTHALF_1`"]
240    #[inline(always)]
241    pub fn is_inthalf_1(&self) -> bool {
242        **self == INTHALF_A::INTHALF_1
243    }
244}
245impl core::ops::Deref for INTHALF_R {
246    type Target = crate::FieldReader<bool, INTHALF_A>;
247    #[inline(always)]
248    fn deref(&self) -> &Self::Target {
249        &self.0
250    }
251}
252#[doc = "Field `INTHALF` writer - Enable an interrupt when major counter is half complete."]
253pub struct INTHALF_W<'a> {
254    w: &'a mut W,
255}
256impl<'a> INTHALF_W<'a> {
257    #[doc = r"Writes `variant` to the field"]
258    #[inline(always)]
259    pub fn variant(self, variant: INTHALF_A) -> &'a mut W {
260        self.bit(variant.into())
261    }
262    #[doc = "The half-point interrupt is disabled."]
263    #[inline(always)]
264    pub fn inthalf_0(self) -> &'a mut W {
265        self.variant(INTHALF_A::INTHALF_0)
266    }
267    #[doc = "The half-point interrupt is enabled."]
268    #[inline(always)]
269    pub fn inthalf_1(self) -> &'a mut W {
270        self.variant(INTHALF_A::INTHALF_1)
271    }
272    #[doc = r"Sets the field bit"]
273    #[inline(always)]
274    pub fn set_bit(self) -> &'a mut W {
275        self.bit(true)
276    }
277    #[doc = r"Clears the field bit"]
278    #[inline(always)]
279    pub fn clear_bit(self) -> &'a mut W {
280        self.bit(false)
281    }
282    #[doc = r"Writes raw bits to the field"]
283    #[inline(always)]
284    pub fn bit(self, value: bool) -> &'a mut W {
285        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2);
286        self.w
287    }
288}
289#[doc = "Disable Request\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq)]
291pub enum DREQ_A {
292    #[doc = "0: The channel's ERQ bit is not affected."]
293    DREQ_0 = 0,
294    #[doc = "1: The channel's ERQ bit is cleared when the major loop is complete."]
295    DREQ_1 = 1,
296}
297impl From<DREQ_A> for bool {
298    #[inline(always)]
299    fn from(variant: DREQ_A) -> Self {
300        variant as u8 != 0
301    }
302}
303#[doc = "Field `DREQ` reader - Disable Request"]
304pub struct DREQ_R(crate::FieldReader<bool, DREQ_A>);
305impl DREQ_R {
306    #[inline(always)]
307    pub(crate) fn new(bits: bool) -> Self {
308        DREQ_R(crate::FieldReader::new(bits))
309    }
310    #[doc = r"Get enumerated values variant"]
311    #[inline(always)]
312    pub fn variant(&self) -> DREQ_A {
313        match self.bits {
314            false => DREQ_A::DREQ_0,
315            true => DREQ_A::DREQ_1,
316        }
317    }
318    #[doc = "Checks if the value of the field is `DREQ_0`"]
319    #[inline(always)]
320    pub fn is_dreq_0(&self) -> bool {
321        **self == DREQ_A::DREQ_0
322    }
323    #[doc = "Checks if the value of the field is `DREQ_1`"]
324    #[inline(always)]
325    pub fn is_dreq_1(&self) -> bool {
326        **self == DREQ_A::DREQ_1
327    }
328}
329impl core::ops::Deref for DREQ_R {
330    type Target = crate::FieldReader<bool, DREQ_A>;
331    #[inline(always)]
332    fn deref(&self) -> &Self::Target {
333        &self.0
334    }
335}
336#[doc = "Field `DREQ` writer - Disable Request"]
337pub struct DREQ_W<'a> {
338    w: &'a mut W,
339}
340impl<'a> DREQ_W<'a> {
341    #[doc = r"Writes `variant` to the field"]
342    #[inline(always)]
343    pub fn variant(self, variant: DREQ_A) -> &'a mut W {
344        self.bit(variant.into())
345    }
346    #[doc = "The channel's ERQ bit is not affected."]
347    #[inline(always)]
348    pub fn dreq_0(self) -> &'a mut W {
349        self.variant(DREQ_A::DREQ_0)
350    }
351    #[doc = "The channel's ERQ bit is cleared when the major loop is complete."]
352    #[inline(always)]
353    pub fn dreq_1(self) -> &'a mut W {
354        self.variant(DREQ_A::DREQ_1)
355    }
356    #[doc = r"Sets the field bit"]
357    #[inline(always)]
358    pub fn set_bit(self) -> &'a mut W {
359        self.bit(true)
360    }
361    #[doc = r"Clears the field bit"]
362    #[inline(always)]
363    pub fn clear_bit(self) -> &'a mut W {
364        self.bit(false)
365    }
366    #[doc = r"Writes raw bits to the field"]
367    #[inline(always)]
368    pub fn bit(self, value: bool) -> &'a mut W {
369        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3);
370        self.w
371    }
372}
373#[doc = "Enable Scatter/Gather Processing\n\nValue on reset: 0"]
374#[derive(Clone, Copy, Debug, PartialEq)]
375pub enum ESG_A {
376    #[doc = "0: The current channel's TCD is normal format."]
377    ESG_0 = 0,
378    #[doc = "1: The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."]
379    ESG_1 = 1,
380}
381impl From<ESG_A> for bool {
382    #[inline(always)]
383    fn from(variant: ESG_A) -> Self {
384        variant as u8 != 0
385    }
386}
387#[doc = "Field `ESG` reader - Enable Scatter/Gather Processing"]
388pub struct ESG_R(crate::FieldReader<bool, ESG_A>);
389impl ESG_R {
390    #[inline(always)]
391    pub(crate) fn new(bits: bool) -> Self {
392        ESG_R(crate::FieldReader::new(bits))
393    }
394    #[doc = r"Get enumerated values variant"]
395    #[inline(always)]
396    pub fn variant(&self) -> ESG_A {
397        match self.bits {
398            false => ESG_A::ESG_0,
399            true => ESG_A::ESG_1,
400        }
401    }
402    #[doc = "Checks if the value of the field is `ESG_0`"]
403    #[inline(always)]
404    pub fn is_esg_0(&self) -> bool {
405        **self == ESG_A::ESG_0
406    }
407    #[doc = "Checks if the value of the field is `ESG_1`"]
408    #[inline(always)]
409    pub fn is_esg_1(&self) -> bool {
410        **self == ESG_A::ESG_1
411    }
412}
413impl core::ops::Deref for ESG_R {
414    type Target = crate::FieldReader<bool, ESG_A>;
415    #[inline(always)]
416    fn deref(&self) -> &Self::Target {
417        &self.0
418    }
419}
420#[doc = "Field `ESG` writer - Enable Scatter/Gather Processing"]
421pub struct ESG_W<'a> {
422    w: &'a mut W,
423}
424impl<'a> ESG_W<'a> {
425    #[doc = r"Writes `variant` to the field"]
426    #[inline(always)]
427    pub fn variant(self, variant: ESG_A) -> &'a mut W {
428        self.bit(variant.into())
429    }
430    #[doc = "The current channel's TCD is normal format."]
431    #[inline(always)]
432    pub fn esg_0(self) -> &'a mut W {
433        self.variant(ESG_A::ESG_0)
434    }
435    #[doc = "The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution."]
436    #[inline(always)]
437    pub fn esg_1(self) -> &'a mut W {
438        self.variant(ESG_A::ESG_1)
439    }
440    #[doc = r"Sets the field bit"]
441    #[inline(always)]
442    pub fn set_bit(self) -> &'a mut W {
443        self.bit(true)
444    }
445    #[doc = r"Clears the field bit"]
446    #[inline(always)]
447    pub fn clear_bit(self) -> &'a mut W {
448        self.bit(false)
449    }
450    #[doc = r"Writes raw bits to the field"]
451    #[inline(always)]
452    pub fn bit(self, value: bool) -> &'a mut W {
453        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4);
454        self.w
455    }
456}
457#[doc = "Enable channel-to-channel linking on major loop complete\n\nValue on reset: 0"]
458#[derive(Clone, Copy, Debug, PartialEq)]
459pub enum MAJORELINK_A {
460    #[doc = "0: The channel-to-channel linking is disabled."]
461    MAJORELINK_0 = 0,
462    #[doc = "1: The channel-to-channel linking is enabled."]
463    MAJORELINK_1 = 1,
464}
465impl From<MAJORELINK_A> for bool {
466    #[inline(always)]
467    fn from(variant: MAJORELINK_A) -> Self {
468        variant as u8 != 0
469    }
470}
471#[doc = "Field `MAJORELINK` reader - Enable channel-to-channel linking on major loop complete"]
472pub struct MAJORELINK_R(crate::FieldReader<bool, MAJORELINK_A>);
473impl MAJORELINK_R {
474    #[inline(always)]
475    pub(crate) fn new(bits: bool) -> Self {
476        MAJORELINK_R(crate::FieldReader::new(bits))
477    }
478    #[doc = r"Get enumerated values variant"]
479    #[inline(always)]
480    pub fn variant(&self) -> MAJORELINK_A {
481        match self.bits {
482            false => MAJORELINK_A::MAJORELINK_0,
483            true => MAJORELINK_A::MAJORELINK_1,
484        }
485    }
486    #[doc = "Checks if the value of the field is `MAJORELINK_0`"]
487    #[inline(always)]
488    pub fn is_majorelink_0(&self) -> bool {
489        **self == MAJORELINK_A::MAJORELINK_0
490    }
491    #[doc = "Checks if the value of the field is `MAJORELINK_1`"]
492    #[inline(always)]
493    pub fn is_majorelink_1(&self) -> bool {
494        **self == MAJORELINK_A::MAJORELINK_1
495    }
496}
497impl core::ops::Deref for MAJORELINK_R {
498    type Target = crate::FieldReader<bool, MAJORELINK_A>;
499    #[inline(always)]
500    fn deref(&self) -> &Self::Target {
501        &self.0
502    }
503}
504#[doc = "Field `MAJORELINK` writer - Enable channel-to-channel linking on major loop complete"]
505pub struct MAJORELINK_W<'a> {
506    w: &'a mut W,
507}
508impl<'a> MAJORELINK_W<'a> {
509    #[doc = r"Writes `variant` to the field"]
510    #[inline(always)]
511    pub fn variant(self, variant: MAJORELINK_A) -> &'a mut W {
512        self.bit(variant.into())
513    }
514    #[doc = "The channel-to-channel linking is disabled."]
515    #[inline(always)]
516    pub fn majorelink_0(self) -> &'a mut W {
517        self.variant(MAJORELINK_A::MAJORELINK_0)
518    }
519    #[doc = "The channel-to-channel linking is enabled."]
520    #[inline(always)]
521    pub fn majorelink_1(self) -> &'a mut W {
522        self.variant(MAJORELINK_A::MAJORELINK_1)
523    }
524    #[doc = r"Sets the field bit"]
525    #[inline(always)]
526    pub fn set_bit(self) -> &'a mut W {
527        self.bit(true)
528    }
529    #[doc = r"Clears the field bit"]
530    #[inline(always)]
531    pub fn clear_bit(self) -> &'a mut W {
532        self.bit(false)
533    }
534    #[doc = r"Writes raw bits to the field"]
535    #[inline(always)]
536    pub fn bit(self, value: bool) -> &'a mut W {
537        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5);
538        self.w
539    }
540}
541#[doc = "Field `ACTIVE` reader - Channel Active"]
542pub struct ACTIVE_R(crate::FieldReader<bool, bool>);
543impl ACTIVE_R {
544    #[inline(always)]
545    pub(crate) fn new(bits: bool) -> Self {
546        ACTIVE_R(crate::FieldReader::new(bits))
547    }
548}
549impl core::ops::Deref for ACTIVE_R {
550    type Target = crate::FieldReader<bool, bool>;
551    #[inline(always)]
552    fn deref(&self) -> &Self::Target {
553        &self.0
554    }
555}
556#[doc = "Field `DONE` reader - Channel Done"]
557pub struct DONE_R(crate::FieldReader<bool, bool>);
558impl DONE_R {
559    #[inline(always)]
560    pub(crate) fn new(bits: bool) -> Self {
561        DONE_R(crate::FieldReader::new(bits))
562    }
563}
564impl core::ops::Deref for DONE_R {
565    type Target = crate::FieldReader<bool, bool>;
566    #[inline(always)]
567    fn deref(&self) -> &Self::Target {
568        &self.0
569    }
570}
571#[doc = "Field `DONE` writer - Channel Done"]
572pub struct DONE_W<'a> {
573    w: &'a mut W,
574}
575impl<'a> DONE_W<'a> {
576    #[doc = r"Sets the field bit"]
577    #[inline(always)]
578    pub fn set_bit(self) -> &'a mut W {
579        self.bit(true)
580    }
581    #[doc = r"Clears the field bit"]
582    #[inline(always)]
583    pub fn clear_bit(self) -> &'a mut W {
584        self.bit(false)
585    }
586    #[doc = r"Writes raw bits to the field"]
587    #[inline(always)]
588    pub fn bit(self, value: bool) -> &'a mut W {
589        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7);
590        self.w
591    }
592}
593#[doc = "Field `MAJORLINKCH` reader - Major Loop Link Channel Number"]
594pub struct MAJORLINKCH_R(crate::FieldReader<u8, u8>);
595impl MAJORLINKCH_R {
596    #[inline(always)]
597    pub(crate) fn new(bits: u8) -> Self {
598        MAJORLINKCH_R(crate::FieldReader::new(bits))
599    }
600}
601impl core::ops::Deref for MAJORLINKCH_R {
602    type Target = crate::FieldReader<u8, u8>;
603    #[inline(always)]
604    fn deref(&self) -> &Self::Target {
605        &self.0
606    }
607}
608#[doc = "Field `MAJORLINKCH` writer - Major Loop Link Channel Number"]
609pub struct MAJORLINKCH_W<'a> {
610    w: &'a mut W,
611}
612impl<'a> MAJORLINKCH_W<'a> {
613    #[doc = r"Writes raw bits to the field"]
614    #[inline(always)]
615    pub unsafe fn bits(self, value: u8) -> &'a mut W {
616        self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8);
617        self.w
618    }
619}
620#[doc = "Bandwidth Control\n\nValue on reset: 0"]
621#[derive(Clone, Copy, Debug, PartialEq)]
622#[repr(u8)]
623pub enum BWC_A {
624    #[doc = "0: No eDMA engine stalls."]
625    BWC_0 = 0,
626    #[doc = "2: eDMA engine stalls for 4 cycles after each R/W."]
627    BWC_2 = 2,
628    #[doc = "3: eDMA engine stalls for 8 cycles after each R/W."]
629    BWC_3 = 3,
630}
631impl From<BWC_A> for u8 {
632    #[inline(always)]
633    fn from(variant: BWC_A) -> Self {
634        variant as _
635    }
636}
637#[doc = "Field `BWC` reader - Bandwidth Control"]
638pub struct BWC_R(crate::FieldReader<u8, BWC_A>);
639impl BWC_R {
640    #[inline(always)]
641    pub(crate) fn new(bits: u8) -> Self {
642        BWC_R(crate::FieldReader::new(bits))
643    }
644    #[doc = r"Get enumerated values variant"]
645    #[inline(always)]
646    pub fn variant(&self) -> Option<BWC_A> {
647        match self.bits {
648            0 => Some(BWC_A::BWC_0),
649            2 => Some(BWC_A::BWC_2),
650            3 => Some(BWC_A::BWC_3),
651            _ => None,
652        }
653    }
654    #[doc = "Checks if the value of the field is `BWC_0`"]
655    #[inline(always)]
656    pub fn is_bwc_0(&self) -> bool {
657        **self == BWC_A::BWC_0
658    }
659    #[doc = "Checks if the value of the field is `BWC_2`"]
660    #[inline(always)]
661    pub fn is_bwc_2(&self) -> bool {
662        **self == BWC_A::BWC_2
663    }
664    #[doc = "Checks if the value of the field is `BWC_3`"]
665    #[inline(always)]
666    pub fn is_bwc_3(&self) -> bool {
667        **self == BWC_A::BWC_3
668    }
669}
670impl core::ops::Deref for BWC_R {
671    type Target = crate::FieldReader<u8, BWC_A>;
672    #[inline(always)]
673    fn deref(&self) -> &Self::Target {
674        &self.0
675    }
676}
677#[doc = "Field `BWC` writer - Bandwidth Control"]
678pub struct BWC_W<'a> {
679    w: &'a mut W,
680}
681impl<'a> BWC_W<'a> {
682    #[doc = r"Writes `variant` to the field"]
683    #[inline(always)]
684    pub fn variant(self, variant: BWC_A) -> &'a mut W {
685        unsafe { self.bits(variant.into()) }
686    }
687    #[doc = "No eDMA engine stalls."]
688    #[inline(always)]
689    pub fn bwc_0(self) -> &'a mut W {
690        self.variant(BWC_A::BWC_0)
691    }
692    #[doc = "eDMA engine stalls for 4 cycles after each R/W."]
693    #[inline(always)]
694    pub fn bwc_2(self) -> &'a mut W {
695        self.variant(BWC_A::BWC_2)
696    }
697    #[doc = "eDMA engine stalls for 8 cycles after each R/W."]
698    #[inline(always)]
699    pub fn bwc_3(self) -> &'a mut W {
700        self.variant(BWC_A::BWC_3)
701    }
702    #[doc = r"Writes raw bits to the field"]
703    #[inline(always)]
704    pub unsafe fn bits(self, value: u8) -> &'a mut W {
705        self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u16 & 0x03) << 14);
706        self.w
707    }
708}
709impl R {
710    #[doc = "Bit 0 - Channel Start"]
711    #[inline(always)]
712    pub fn start(&self) -> START_R {
713        START_R::new((self.bits & 0x01) != 0)
714    }
715    #[doc = "Bit 1 - Enable an interrupt when major iteration count completes."]
716    #[inline(always)]
717    pub fn intmajor(&self) -> INTMAJOR_R {
718        INTMAJOR_R::new(((self.bits >> 1) & 0x01) != 0)
719    }
720    #[doc = "Bit 2 - Enable an interrupt when major counter is half complete."]
721    #[inline(always)]
722    pub fn inthalf(&self) -> INTHALF_R {
723        INTHALF_R::new(((self.bits >> 2) & 0x01) != 0)
724    }
725    #[doc = "Bit 3 - Disable Request"]
726    #[inline(always)]
727    pub fn dreq(&self) -> DREQ_R {
728        DREQ_R::new(((self.bits >> 3) & 0x01) != 0)
729    }
730    #[doc = "Bit 4 - Enable Scatter/Gather Processing"]
731    #[inline(always)]
732    pub fn esg(&self) -> ESG_R {
733        ESG_R::new(((self.bits >> 4) & 0x01) != 0)
734    }
735    #[doc = "Bit 5 - Enable channel-to-channel linking on major loop complete"]
736    #[inline(always)]
737    pub fn majorelink(&self) -> MAJORELINK_R {
738        MAJORELINK_R::new(((self.bits >> 5) & 0x01) != 0)
739    }
740    #[doc = "Bit 6 - Channel Active"]
741    #[inline(always)]
742    pub fn active(&self) -> ACTIVE_R {
743        ACTIVE_R::new(((self.bits >> 6) & 0x01) != 0)
744    }
745    #[doc = "Bit 7 - Channel Done"]
746    #[inline(always)]
747    pub fn done(&self) -> DONE_R {
748        DONE_R::new(((self.bits >> 7) & 0x01) != 0)
749    }
750    #[doc = "Bits 8:11 - Major Loop Link Channel Number"]
751    #[inline(always)]
752    pub fn majorlinkch(&self) -> MAJORLINKCH_R {
753        MAJORLINKCH_R::new(((self.bits >> 8) & 0x0f) as u8)
754    }
755    #[doc = "Bits 14:15 - Bandwidth Control"]
756    #[inline(always)]
757    pub fn bwc(&self) -> BWC_R {
758        BWC_R::new(((self.bits >> 14) & 0x03) as u8)
759    }
760}
761impl W {
762    #[doc = "Bit 0 - Channel Start"]
763    #[inline(always)]
764    pub fn start(&mut self) -> START_W {
765        START_W { w: self }
766    }
767    #[doc = "Bit 1 - Enable an interrupt when major iteration count completes."]
768    #[inline(always)]
769    pub fn intmajor(&mut self) -> INTMAJOR_W {
770        INTMAJOR_W { w: self }
771    }
772    #[doc = "Bit 2 - Enable an interrupt when major counter is half complete."]
773    #[inline(always)]
774    pub fn inthalf(&mut self) -> INTHALF_W {
775        INTHALF_W { w: self }
776    }
777    #[doc = "Bit 3 - Disable Request"]
778    #[inline(always)]
779    pub fn dreq(&mut self) -> DREQ_W {
780        DREQ_W { w: self }
781    }
782    #[doc = "Bit 4 - Enable Scatter/Gather Processing"]
783    #[inline(always)]
784    pub fn esg(&mut self) -> ESG_W {
785        ESG_W { w: self }
786    }
787    #[doc = "Bit 5 - Enable channel-to-channel linking on major loop complete"]
788    #[inline(always)]
789    pub fn majorelink(&mut self) -> MAJORELINK_W {
790        MAJORELINK_W { w: self }
791    }
792    #[doc = "Bit 7 - Channel Done"]
793    #[inline(always)]
794    pub fn done(&mut self) -> DONE_W {
795        DONE_W { w: self }
796    }
797    #[doc = "Bits 8:11 - Major Loop Link Channel Number"]
798    #[inline(always)]
799    pub fn majorlinkch(&mut self) -> MAJORLINKCH_W {
800        MAJORLINKCH_W { w: self }
801    }
802    #[doc = "Bits 14:15 - Bandwidth Control"]
803    #[inline(always)]
804    pub fn bwc(&mut self) -> BWC_W {
805        BWC_W { w: self }
806    }
807    #[doc = "Writes raw bits to the register."]
808    #[inline(always)]
809    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
810        self.0.bits(bits);
811        self
812    }
813}
814#[doc = "TCD Control and Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcd6_csr](index.html) module"]
815pub struct TCD6_CSR_SPEC;
816impl crate::RegisterSpec for TCD6_CSR_SPEC {
817    type Ux = u16;
818}
819#[doc = "`read()` method returns [tcd6_csr::R](R) reader structure"]
820impl crate::Readable for TCD6_CSR_SPEC {
821    type Reader = R;
822}
823#[doc = "`write(|w| ..)` method takes [tcd6_csr::W](W) writer structure"]
824impl crate::Writable for TCD6_CSR_SPEC {
825    type Writer = W;
826}
827#[doc = "`reset()` method sets TCD6_CSR to value 0"]
828impl crate::Resettable for TCD6_CSR_SPEC {
829    #[inline(always)]
830    fn reset_value() -> Self::Ux {
831        0
832    }
833}
s32k144w_pac/dma/tcd6_csr.rs

s32k144w_pac/dma/
tcd6_csr.rs
