1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::COMBINE {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R { bits: self.register.get() }
26 }
27 #[doc = r" Writes to the register"]
28 #[inline]
29 pub fn write<F>(&self, f: F)
30 where
31 F: FnOnce(&mut W) -> &mut W,
32 {
33 let mut w = W::reset_value();
34 f(&mut w);
35 self.register.set(w.bits);
36 }
37 #[doc = r" Writes the reset value to the register"]
38 #[inline]
39 pub fn reset(&self) {
40 self.write(|w| w)
41 }
42}
43#[doc = r" Value of the field"]
44pub struct COMBINE0R {
45 bits: bool,
46}
47impl COMBINE0R {
48 #[doc = r" Value of the field as raw bits"]
49 #[inline]
50 pub fn bit(&self) -> bool {
51 self.bits
52 }
53 #[doc = r" Returns `true` if the bit is clear (0)"]
54 #[inline]
55 pub fn bit_is_clear(&self) -> bool {
56 !self.bit()
57 }
58 #[doc = r" Returns `true` if the bit is set (1)"]
59 #[inline]
60 pub fn bit_is_set(&self) -> bool {
61 self.bit()
62 }
63}
64#[doc = "Possible values of the field `COMP0`"]
65#[derive(Clone, Copy, Debug, PartialEq)]
66pub enum COMP0R {
67 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
68 _0,
69 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
70 _1,
71}
72impl COMP0R {
73 #[doc = r" Returns `true` if the bit is clear (0)"]
74 #[inline]
75 pub fn bit_is_clear(&self) -> bool {
76 !self.bit()
77 }
78 #[doc = r" Returns `true` if the bit is set (1)"]
79 #[inline]
80 pub fn bit_is_set(&self) -> bool {
81 self.bit()
82 }
83 #[doc = r" Value of the field as raw bits"]
84 #[inline]
85 pub fn bit(&self) -> bool {
86 match *self {
87 COMP0R::_0 => false,
88 COMP0R::_1 => true,
89 }
90 }
91 #[allow(missing_docs)]
92 #[doc(hidden)]
93 #[inline]
94 pub fn _from(value: bool) -> COMP0R {
95 match value {
96 false => COMP0R::_0,
97 true => COMP0R::_1,
98 }
99 }
100 #[doc = "Checks if the value of the field is `_0`"]
101 #[inline]
102 pub fn is_0(&self) -> bool {
103 *self == COMP0R::_0
104 }
105 #[doc = "Checks if the value of the field is `_1`"]
106 #[inline]
107 pub fn is_1(&self) -> bool {
108 *self == COMP0R::_1
109 }
110}
111#[doc = r" Value of the field"]
112pub struct DECAPEN0R {
113 bits: bool,
114}
115impl DECAPEN0R {
116 #[doc = r" Value of the field as raw bits"]
117 #[inline]
118 pub fn bit(&self) -> bool {
119 self.bits
120 }
121 #[doc = r" Returns `true` if the bit is clear (0)"]
122 #[inline]
123 pub fn bit_is_clear(&self) -> bool {
124 !self.bit()
125 }
126 #[doc = r" Returns `true` if the bit is set (1)"]
127 #[inline]
128 pub fn bit_is_set(&self) -> bool {
129 self.bit()
130 }
131}
132#[doc = "Possible values of the field `DECAP0`"]
133#[derive(Clone, Copy, Debug, PartialEq)]
134pub enum DECAP0R {
135 #[doc = "The dual edge captures are inactive."]
136 _0,
137 #[doc = "The dual edge captures are active."]
138 _1,
139}
140impl DECAP0R {
141 #[doc = r" Returns `true` if the bit is clear (0)"]
142 #[inline]
143 pub fn bit_is_clear(&self) -> bool {
144 !self.bit()
145 }
146 #[doc = r" Returns `true` if the bit is set (1)"]
147 #[inline]
148 pub fn bit_is_set(&self) -> bool {
149 self.bit()
150 }
151 #[doc = r" Value of the field as raw bits"]
152 #[inline]
153 pub fn bit(&self) -> bool {
154 match *self {
155 DECAP0R::_0 => false,
156 DECAP0R::_1 => true,
157 }
158 }
159 #[allow(missing_docs)]
160 #[doc(hidden)]
161 #[inline]
162 pub fn _from(value: bool) -> DECAP0R {
163 match value {
164 false => DECAP0R::_0,
165 true => DECAP0R::_1,
166 }
167 }
168 #[doc = "Checks if the value of the field is `_0`"]
169 #[inline]
170 pub fn is_0(&self) -> bool {
171 *self == DECAP0R::_0
172 }
173 #[doc = "Checks if the value of the field is `_1`"]
174 #[inline]
175 pub fn is_1(&self) -> bool {
176 *self == DECAP0R::_1
177 }
178}
179#[doc = "Possible values of the field `DTEN0`"]
180#[derive(Clone, Copy, Debug, PartialEq)]
181pub enum DTEN0R {
182 #[doc = "The deadtime insertion in this pair of channels is disabled."]
183 _0,
184 #[doc = "The deadtime insertion in this pair of channels is enabled."]
185 _1,
186}
187impl DTEN0R {
188 #[doc = r" Returns `true` if the bit is clear (0)"]
189 #[inline]
190 pub fn bit_is_clear(&self) -> bool {
191 !self.bit()
192 }
193 #[doc = r" Returns `true` if the bit is set (1)"]
194 #[inline]
195 pub fn bit_is_set(&self) -> bool {
196 self.bit()
197 }
198 #[doc = r" Value of the field as raw bits"]
199 #[inline]
200 pub fn bit(&self) -> bool {
201 match *self {
202 DTEN0R::_0 => false,
203 DTEN0R::_1 => true,
204 }
205 }
206 #[allow(missing_docs)]
207 #[doc(hidden)]
208 #[inline]
209 pub fn _from(value: bool) -> DTEN0R {
210 match value {
211 false => DTEN0R::_0,
212 true => DTEN0R::_1,
213 }
214 }
215 #[doc = "Checks if the value of the field is `_0`"]
216 #[inline]
217 pub fn is_0(&self) -> bool {
218 *self == DTEN0R::_0
219 }
220 #[doc = "Checks if the value of the field is `_1`"]
221 #[inline]
222 pub fn is_1(&self) -> bool {
223 *self == DTEN0R::_1
224 }
225}
226#[doc = "Possible values of the field `SYNCEN0`"]
227#[derive(Clone, Copy, Debug, PartialEq)]
228pub enum SYNCEN0R {
229 #[doc = "The PWM synchronization in this pair of channels is disabled."]
230 _0,
231 #[doc = "The PWM synchronization in this pair of channels is enabled."]
232 _1,
233}
234impl SYNCEN0R {
235 #[doc = r" Returns `true` if the bit is clear (0)"]
236 #[inline]
237 pub fn bit_is_clear(&self) -> bool {
238 !self.bit()
239 }
240 #[doc = r" Returns `true` if the bit is set (1)"]
241 #[inline]
242 pub fn bit_is_set(&self) -> bool {
243 self.bit()
244 }
245 #[doc = r" Value of the field as raw bits"]
246 #[inline]
247 pub fn bit(&self) -> bool {
248 match *self {
249 SYNCEN0R::_0 => false,
250 SYNCEN0R::_1 => true,
251 }
252 }
253 #[allow(missing_docs)]
254 #[doc(hidden)]
255 #[inline]
256 pub fn _from(value: bool) -> SYNCEN0R {
257 match value {
258 false => SYNCEN0R::_0,
259 true => SYNCEN0R::_1,
260 }
261 }
262 #[doc = "Checks if the value of the field is `_0`"]
263 #[inline]
264 pub fn is_0(&self) -> bool {
265 *self == SYNCEN0R::_0
266 }
267 #[doc = "Checks if the value of the field is `_1`"]
268 #[inline]
269 pub fn is_1(&self) -> bool {
270 *self == SYNCEN0R::_1
271 }
272}
273#[doc = "Possible values of the field `FAULTEN0`"]
274#[derive(Clone, Copy, Debug, PartialEq)]
275pub enum FAULTEN0R {
276 #[doc = "The fault control in this pair of channels is disabled."]
277 _0,
278 #[doc = "The fault control in this pair of channels is enabled."]
279 _1,
280}
281impl FAULTEN0R {
282 #[doc = r" Returns `true` if the bit is clear (0)"]
283 #[inline]
284 pub fn bit_is_clear(&self) -> bool {
285 !self.bit()
286 }
287 #[doc = r" Returns `true` if the bit is set (1)"]
288 #[inline]
289 pub fn bit_is_set(&self) -> bool {
290 self.bit()
291 }
292 #[doc = r" Value of the field as raw bits"]
293 #[inline]
294 pub fn bit(&self) -> bool {
295 match *self {
296 FAULTEN0R::_0 => false,
297 FAULTEN0R::_1 => true,
298 }
299 }
300 #[allow(missing_docs)]
301 #[doc(hidden)]
302 #[inline]
303 pub fn _from(value: bool) -> FAULTEN0R {
304 match value {
305 false => FAULTEN0R::_0,
306 true => FAULTEN0R::_1,
307 }
308 }
309 #[doc = "Checks if the value of the field is `_0`"]
310 #[inline]
311 pub fn is_0(&self) -> bool {
312 *self == FAULTEN0R::_0
313 }
314 #[doc = "Checks if the value of the field is `_1`"]
315 #[inline]
316 pub fn is_1(&self) -> bool {
317 *self == FAULTEN0R::_1
318 }
319}
320#[doc = r" Value of the field"]
321pub struct MCOMBINE0R {
322 bits: bool,
323}
324impl MCOMBINE0R {
325 #[doc = r" Value of the field as raw bits"]
326 #[inline]
327 pub fn bit(&self) -> bool {
328 self.bits
329 }
330 #[doc = r" Returns `true` if the bit is clear (0)"]
331 #[inline]
332 pub fn bit_is_clear(&self) -> bool {
333 !self.bit()
334 }
335 #[doc = r" Returns `true` if the bit is set (1)"]
336 #[inline]
337 pub fn bit_is_set(&self) -> bool {
338 self.bit()
339 }
340}
341#[doc = r" Value of the field"]
342pub struct COMBINE1R {
343 bits: bool,
344}
345impl COMBINE1R {
346 #[doc = r" Value of the field as raw bits"]
347 #[inline]
348 pub fn bit(&self) -> bool {
349 self.bits
350 }
351 #[doc = r" Returns `true` if the bit is clear (0)"]
352 #[inline]
353 pub fn bit_is_clear(&self) -> bool {
354 !self.bit()
355 }
356 #[doc = r" Returns `true` if the bit is set (1)"]
357 #[inline]
358 pub fn bit_is_set(&self) -> bool {
359 self.bit()
360 }
361}
362#[doc = "Possible values of the field `COMP1`"]
363#[derive(Clone, Copy, Debug, PartialEq)]
364pub enum COMP1R {
365 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
366 _0,
367 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
368 _1,
369}
370impl COMP1R {
371 #[doc = r" Returns `true` if the bit is clear (0)"]
372 #[inline]
373 pub fn bit_is_clear(&self) -> bool {
374 !self.bit()
375 }
376 #[doc = r" Returns `true` if the bit is set (1)"]
377 #[inline]
378 pub fn bit_is_set(&self) -> bool {
379 self.bit()
380 }
381 #[doc = r" Value of the field as raw bits"]
382 #[inline]
383 pub fn bit(&self) -> bool {
384 match *self {
385 COMP1R::_0 => false,
386 COMP1R::_1 => true,
387 }
388 }
389 #[allow(missing_docs)]
390 #[doc(hidden)]
391 #[inline]
392 pub fn _from(value: bool) -> COMP1R {
393 match value {
394 false => COMP1R::_0,
395 true => COMP1R::_1,
396 }
397 }
398 #[doc = "Checks if the value of the field is `_0`"]
399 #[inline]
400 pub fn is_0(&self) -> bool {
401 *self == COMP1R::_0
402 }
403 #[doc = "Checks if the value of the field is `_1`"]
404 #[inline]
405 pub fn is_1(&self) -> bool {
406 *self == COMP1R::_1
407 }
408}
409#[doc = r" Value of the field"]
410pub struct DECAPEN1R {
411 bits: bool,
412}
413impl DECAPEN1R {
414 #[doc = r" Value of the field as raw bits"]
415 #[inline]
416 pub fn bit(&self) -> bool {
417 self.bits
418 }
419 #[doc = r" Returns `true` if the bit is clear (0)"]
420 #[inline]
421 pub fn bit_is_clear(&self) -> bool {
422 !self.bit()
423 }
424 #[doc = r" Returns `true` if the bit is set (1)"]
425 #[inline]
426 pub fn bit_is_set(&self) -> bool {
427 self.bit()
428 }
429}
430#[doc = "Possible values of the field `DECAP1`"]
431#[derive(Clone, Copy, Debug, PartialEq)]
432pub enum DECAP1R {
433 #[doc = "The dual edge captures are inactive."]
434 _0,
435 #[doc = "The dual edge captures are active."]
436 _1,
437}
438impl DECAP1R {
439 #[doc = r" Returns `true` if the bit is clear (0)"]
440 #[inline]
441 pub fn bit_is_clear(&self) -> bool {
442 !self.bit()
443 }
444 #[doc = r" Returns `true` if the bit is set (1)"]
445 #[inline]
446 pub fn bit_is_set(&self) -> bool {
447 self.bit()
448 }
449 #[doc = r" Value of the field as raw bits"]
450 #[inline]
451 pub fn bit(&self) -> bool {
452 match *self {
453 DECAP1R::_0 => false,
454 DECAP1R::_1 => true,
455 }
456 }
457 #[allow(missing_docs)]
458 #[doc(hidden)]
459 #[inline]
460 pub fn _from(value: bool) -> DECAP1R {
461 match value {
462 false => DECAP1R::_0,
463 true => DECAP1R::_1,
464 }
465 }
466 #[doc = "Checks if the value of the field is `_0`"]
467 #[inline]
468 pub fn is_0(&self) -> bool {
469 *self == DECAP1R::_0
470 }
471 #[doc = "Checks if the value of the field is `_1`"]
472 #[inline]
473 pub fn is_1(&self) -> bool {
474 *self == DECAP1R::_1
475 }
476}
477#[doc = "Possible values of the field `DTEN1`"]
478#[derive(Clone, Copy, Debug, PartialEq)]
479pub enum DTEN1R {
480 #[doc = "The deadtime insertion in this pair of channels is disabled."]
481 _0,
482 #[doc = "The deadtime insertion in this pair of channels is enabled."]
483 _1,
484}
485impl DTEN1R {
486 #[doc = r" Returns `true` if the bit is clear (0)"]
487 #[inline]
488 pub fn bit_is_clear(&self) -> bool {
489 !self.bit()
490 }
491 #[doc = r" Returns `true` if the bit is set (1)"]
492 #[inline]
493 pub fn bit_is_set(&self) -> bool {
494 self.bit()
495 }
496 #[doc = r" Value of the field as raw bits"]
497 #[inline]
498 pub fn bit(&self) -> bool {
499 match *self {
500 DTEN1R::_0 => false,
501 DTEN1R::_1 => true,
502 }
503 }
504 #[allow(missing_docs)]
505 #[doc(hidden)]
506 #[inline]
507 pub fn _from(value: bool) -> DTEN1R {
508 match value {
509 false => DTEN1R::_0,
510 true => DTEN1R::_1,
511 }
512 }
513 #[doc = "Checks if the value of the field is `_0`"]
514 #[inline]
515 pub fn is_0(&self) -> bool {
516 *self == DTEN1R::_0
517 }
518 #[doc = "Checks if the value of the field is `_1`"]
519 #[inline]
520 pub fn is_1(&self) -> bool {
521 *self == DTEN1R::_1
522 }
523}
524#[doc = "Possible values of the field `SYNCEN1`"]
525#[derive(Clone, Copy, Debug, PartialEq)]
526pub enum SYNCEN1R {
527 #[doc = "The PWM synchronization in this pair of channels is disabled."]
528 _0,
529 #[doc = "The PWM synchronization in this pair of channels is enabled."]
530 _1,
531}
532impl SYNCEN1R {
533 #[doc = r" Returns `true` if the bit is clear (0)"]
534 #[inline]
535 pub fn bit_is_clear(&self) -> bool {
536 !self.bit()
537 }
538 #[doc = r" Returns `true` if the bit is set (1)"]
539 #[inline]
540 pub fn bit_is_set(&self) -> bool {
541 self.bit()
542 }
543 #[doc = r" Value of the field as raw bits"]
544 #[inline]
545 pub fn bit(&self) -> bool {
546 match *self {
547 SYNCEN1R::_0 => false,
548 SYNCEN1R::_1 => true,
549 }
550 }
551 #[allow(missing_docs)]
552 #[doc(hidden)]
553 #[inline]
554 pub fn _from(value: bool) -> SYNCEN1R {
555 match value {
556 false => SYNCEN1R::_0,
557 true => SYNCEN1R::_1,
558 }
559 }
560 #[doc = "Checks if the value of the field is `_0`"]
561 #[inline]
562 pub fn is_0(&self) -> bool {
563 *self == SYNCEN1R::_0
564 }
565 #[doc = "Checks if the value of the field is `_1`"]
566 #[inline]
567 pub fn is_1(&self) -> bool {
568 *self == SYNCEN1R::_1
569 }
570}
571#[doc = "Possible values of the field `FAULTEN1`"]
572#[derive(Clone, Copy, Debug, PartialEq)]
573pub enum FAULTEN1R {
574 #[doc = "The fault control in this pair of channels is disabled."]
575 _0,
576 #[doc = "The fault control in this pair of channels is enabled."]
577 _1,
578}
579impl FAULTEN1R {
580 #[doc = r" Returns `true` if the bit is clear (0)"]
581 #[inline]
582 pub fn bit_is_clear(&self) -> bool {
583 !self.bit()
584 }
585 #[doc = r" Returns `true` if the bit is set (1)"]
586 #[inline]
587 pub fn bit_is_set(&self) -> bool {
588 self.bit()
589 }
590 #[doc = r" Value of the field as raw bits"]
591 #[inline]
592 pub fn bit(&self) -> bool {
593 match *self {
594 FAULTEN1R::_0 => false,
595 FAULTEN1R::_1 => true,
596 }
597 }
598 #[allow(missing_docs)]
599 #[doc(hidden)]
600 #[inline]
601 pub fn _from(value: bool) -> FAULTEN1R {
602 match value {
603 false => FAULTEN1R::_0,
604 true => FAULTEN1R::_1,
605 }
606 }
607 #[doc = "Checks if the value of the field is `_0`"]
608 #[inline]
609 pub fn is_0(&self) -> bool {
610 *self == FAULTEN1R::_0
611 }
612 #[doc = "Checks if the value of the field is `_1`"]
613 #[inline]
614 pub fn is_1(&self) -> bool {
615 *self == FAULTEN1R::_1
616 }
617}
618#[doc = r" Value of the field"]
619pub struct MCOMBINE1R {
620 bits: bool,
621}
622impl MCOMBINE1R {
623 #[doc = r" Value of the field as raw bits"]
624 #[inline]
625 pub fn bit(&self) -> bool {
626 self.bits
627 }
628 #[doc = r" Returns `true` if the bit is clear (0)"]
629 #[inline]
630 pub fn bit_is_clear(&self) -> bool {
631 !self.bit()
632 }
633 #[doc = r" Returns `true` if the bit is set (1)"]
634 #[inline]
635 pub fn bit_is_set(&self) -> bool {
636 self.bit()
637 }
638}
639#[doc = r" Value of the field"]
640pub struct COMBINE2R {
641 bits: bool,
642}
643impl COMBINE2R {
644 #[doc = r" Value of the field as raw bits"]
645 #[inline]
646 pub fn bit(&self) -> bool {
647 self.bits
648 }
649 #[doc = r" Returns `true` if the bit is clear (0)"]
650 #[inline]
651 pub fn bit_is_clear(&self) -> bool {
652 !self.bit()
653 }
654 #[doc = r" Returns `true` if the bit is set (1)"]
655 #[inline]
656 pub fn bit_is_set(&self) -> bool {
657 self.bit()
658 }
659}
660#[doc = "Possible values of the field `COMP2`"]
661#[derive(Clone, Copy, Debug, PartialEq)]
662pub enum COMP2R {
663 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
664 _0,
665 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
666 _1,
667}
668impl COMP2R {
669 #[doc = r" Returns `true` if the bit is clear (0)"]
670 #[inline]
671 pub fn bit_is_clear(&self) -> bool {
672 !self.bit()
673 }
674 #[doc = r" Returns `true` if the bit is set (1)"]
675 #[inline]
676 pub fn bit_is_set(&self) -> bool {
677 self.bit()
678 }
679 #[doc = r" Value of the field as raw bits"]
680 #[inline]
681 pub fn bit(&self) -> bool {
682 match *self {
683 COMP2R::_0 => false,
684 COMP2R::_1 => true,
685 }
686 }
687 #[allow(missing_docs)]
688 #[doc(hidden)]
689 #[inline]
690 pub fn _from(value: bool) -> COMP2R {
691 match value {
692 false => COMP2R::_0,
693 true => COMP2R::_1,
694 }
695 }
696 #[doc = "Checks if the value of the field is `_0`"]
697 #[inline]
698 pub fn is_0(&self) -> bool {
699 *self == COMP2R::_0
700 }
701 #[doc = "Checks if the value of the field is `_1`"]
702 #[inline]
703 pub fn is_1(&self) -> bool {
704 *self == COMP2R::_1
705 }
706}
707#[doc = r" Value of the field"]
708pub struct DECAPEN2R {
709 bits: bool,
710}
711impl DECAPEN2R {
712 #[doc = r" Value of the field as raw bits"]
713 #[inline]
714 pub fn bit(&self) -> bool {
715 self.bits
716 }
717 #[doc = r" Returns `true` if the bit is clear (0)"]
718 #[inline]
719 pub fn bit_is_clear(&self) -> bool {
720 !self.bit()
721 }
722 #[doc = r" Returns `true` if the bit is set (1)"]
723 #[inline]
724 pub fn bit_is_set(&self) -> bool {
725 self.bit()
726 }
727}
728#[doc = "Possible values of the field `DECAP2`"]
729#[derive(Clone, Copy, Debug, PartialEq)]
730pub enum DECAP2R {
731 #[doc = "The dual edge captures are inactive."]
732 _0,
733 #[doc = "The dual edge captures are active."]
734 _1,
735}
736impl DECAP2R {
737 #[doc = r" Returns `true` if the bit is clear (0)"]
738 #[inline]
739 pub fn bit_is_clear(&self) -> bool {
740 !self.bit()
741 }
742 #[doc = r" Returns `true` if the bit is set (1)"]
743 #[inline]
744 pub fn bit_is_set(&self) -> bool {
745 self.bit()
746 }
747 #[doc = r" Value of the field as raw bits"]
748 #[inline]
749 pub fn bit(&self) -> bool {
750 match *self {
751 DECAP2R::_0 => false,
752 DECAP2R::_1 => true,
753 }
754 }
755 #[allow(missing_docs)]
756 #[doc(hidden)]
757 #[inline]
758 pub fn _from(value: bool) -> DECAP2R {
759 match value {
760 false => DECAP2R::_0,
761 true => DECAP2R::_1,
762 }
763 }
764 #[doc = "Checks if the value of the field is `_0`"]
765 #[inline]
766 pub fn is_0(&self) -> bool {
767 *self == DECAP2R::_0
768 }
769 #[doc = "Checks if the value of the field is `_1`"]
770 #[inline]
771 pub fn is_1(&self) -> bool {
772 *self == DECAP2R::_1
773 }
774}
775#[doc = "Possible values of the field `DTEN2`"]
776#[derive(Clone, Copy, Debug, PartialEq)]
777pub enum DTEN2R {
778 #[doc = "The deadtime insertion in this pair of channels is disabled."]
779 _0,
780 #[doc = "The deadtime insertion in this pair of channels is enabled."]
781 _1,
782}
783impl DTEN2R {
784 #[doc = r" Returns `true` if the bit is clear (0)"]
785 #[inline]
786 pub fn bit_is_clear(&self) -> bool {
787 !self.bit()
788 }
789 #[doc = r" Returns `true` if the bit is set (1)"]
790 #[inline]
791 pub fn bit_is_set(&self) -> bool {
792 self.bit()
793 }
794 #[doc = r" Value of the field as raw bits"]
795 #[inline]
796 pub fn bit(&self) -> bool {
797 match *self {
798 DTEN2R::_0 => false,
799 DTEN2R::_1 => true,
800 }
801 }
802 #[allow(missing_docs)]
803 #[doc(hidden)]
804 #[inline]
805 pub fn _from(value: bool) -> DTEN2R {
806 match value {
807 false => DTEN2R::_0,
808 true => DTEN2R::_1,
809 }
810 }
811 #[doc = "Checks if the value of the field is `_0`"]
812 #[inline]
813 pub fn is_0(&self) -> bool {
814 *self == DTEN2R::_0
815 }
816 #[doc = "Checks if the value of the field is `_1`"]
817 #[inline]
818 pub fn is_1(&self) -> bool {
819 *self == DTEN2R::_1
820 }
821}
822#[doc = "Possible values of the field `SYNCEN2`"]
823#[derive(Clone, Copy, Debug, PartialEq)]
824pub enum SYNCEN2R {
825 #[doc = "The PWM synchronization in this pair of channels is disabled."]
826 _0,
827 #[doc = "The PWM synchronization in this pair of channels is enabled."]
828 _1,
829}
830impl SYNCEN2R {
831 #[doc = r" Returns `true` if the bit is clear (0)"]
832 #[inline]
833 pub fn bit_is_clear(&self) -> bool {
834 !self.bit()
835 }
836 #[doc = r" Returns `true` if the bit is set (1)"]
837 #[inline]
838 pub fn bit_is_set(&self) -> bool {
839 self.bit()
840 }
841 #[doc = r" Value of the field as raw bits"]
842 #[inline]
843 pub fn bit(&self) -> bool {
844 match *self {
845 SYNCEN2R::_0 => false,
846 SYNCEN2R::_1 => true,
847 }
848 }
849 #[allow(missing_docs)]
850 #[doc(hidden)]
851 #[inline]
852 pub fn _from(value: bool) -> SYNCEN2R {
853 match value {
854 false => SYNCEN2R::_0,
855 true => SYNCEN2R::_1,
856 }
857 }
858 #[doc = "Checks if the value of the field is `_0`"]
859 #[inline]
860 pub fn is_0(&self) -> bool {
861 *self == SYNCEN2R::_0
862 }
863 #[doc = "Checks if the value of the field is `_1`"]
864 #[inline]
865 pub fn is_1(&self) -> bool {
866 *self == SYNCEN2R::_1
867 }
868}
869#[doc = "Possible values of the field `FAULTEN2`"]
870#[derive(Clone, Copy, Debug, PartialEq)]
871pub enum FAULTEN2R {
872 #[doc = "The fault control in this pair of channels is disabled."]
873 _0,
874 #[doc = "The fault control in this pair of channels is enabled."]
875 _1,
876}
877impl FAULTEN2R {
878 #[doc = r" Returns `true` if the bit is clear (0)"]
879 #[inline]
880 pub fn bit_is_clear(&self) -> bool {
881 !self.bit()
882 }
883 #[doc = r" Returns `true` if the bit is set (1)"]
884 #[inline]
885 pub fn bit_is_set(&self) -> bool {
886 self.bit()
887 }
888 #[doc = r" Value of the field as raw bits"]
889 #[inline]
890 pub fn bit(&self) -> bool {
891 match *self {
892 FAULTEN2R::_0 => false,
893 FAULTEN2R::_1 => true,
894 }
895 }
896 #[allow(missing_docs)]
897 #[doc(hidden)]
898 #[inline]
899 pub fn _from(value: bool) -> FAULTEN2R {
900 match value {
901 false => FAULTEN2R::_0,
902 true => FAULTEN2R::_1,
903 }
904 }
905 #[doc = "Checks if the value of the field is `_0`"]
906 #[inline]
907 pub fn is_0(&self) -> bool {
908 *self == FAULTEN2R::_0
909 }
910 #[doc = "Checks if the value of the field is `_1`"]
911 #[inline]
912 pub fn is_1(&self) -> bool {
913 *self == FAULTEN2R::_1
914 }
915}
916#[doc = r" Value of the field"]
917pub struct MCOMBINE2R {
918 bits: bool,
919}
920impl MCOMBINE2R {
921 #[doc = r" Value of the field as raw bits"]
922 #[inline]
923 pub fn bit(&self) -> bool {
924 self.bits
925 }
926 #[doc = r" Returns `true` if the bit is clear (0)"]
927 #[inline]
928 pub fn bit_is_clear(&self) -> bool {
929 !self.bit()
930 }
931 #[doc = r" Returns `true` if the bit is set (1)"]
932 #[inline]
933 pub fn bit_is_set(&self) -> bool {
934 self.bit()
935 }
936}
937#[doc = r" Value of the field"]
938pub struct COMBINE3R {
939 bits: bool,
940}
941impl COMBINE3R {
942 #[doc = r" Value of the field as raw bits"]
943 #[inline]
944 pub fn bit(&self) -> bool {
945 self.bits
946 }
947 #[doc = r" Returns `true` if the bit is clear (0)"]
948 #[inline]
949 pub fn bit_is_clear(&self) -> bool {
950 !self.bit()
951 }
952 #[doc = r" Returns `true` if the bit is set (1)"]
953 #[inline]
954 pub fn bit_is_set(&self) -> bool {
955 self.bit()
956 }
957}
958#[doc = "Possible values of the field `COMP3`"]
959#[derive(Clone, Copy, Debug, PartialEq)]
960pub enum COMP3R {
961 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
962 _0,
963 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
964 _1,
965}
966impl COMP3R {
967 #[doc = r" Returns `true` if the bit is clear (0)"]
968 #[inline]
969 pub fn bit_is_clear(&self) -> bool {
970 !self.bit()
971 }
972 #[doc = r" Returns `true` if the bit is set (1)"]
973 #[inline]
974 pub fn bit_is_set(&self) -> bool {
975 self.bit()
976 }
977 #[doc = r" Value of the field as raw bits"]
978 #[inline]
979 pub fn bit(&self) -> bool {
980 match *self {
981 COMP3R::_0 => false,
982 COMP3R::_1 => true,
983 }
984 }
985 #[allow(missing_docs)]
986 #[doc(hidden)]
987 #[inline]
988 pub fn _from(value: bool) -> COMP3R {
989 match value {
990 false => COMP3R::_0,
991 true => COMP3R::_1,
992 }
993 }
994 #[doc = "Checks if the value of the field is `_0`"]
995 #[inline]
996 pub fn is_0(&self) -> bool {
997 *self == COMP3R::_0
998 }
999 #[doc = "Checks if the value of the field is `_1`"]
1000 #[inline]
1001 pub fn is_1(&self) -> bool {
1002 *self == COMP3R::_1
1003 }
1004}
1005#[doc = r" Value of the field"]
1006pub struct DECAPEN3R {
1007 bits: bool,
1008}
1009impl DECAPEN3R {
1010 #[doc = r" Value of the field as raw bits"]
1011 #[inline]
1012 pub fn bit(&self) -> bool {
1013 self.bits
1014 }
1015 #[doc = r" Returns `true` if the bit is clear (0)"]
1016 #[inline]
1017 pub fn bit_is_clear(&self) -> bool {
1018 !self.bit()
1019 }
1020 #[doc = r" Returns `true` if the bit is set (1)"]
1021 #[inline]
1022 pub fn bit_is_set(&self) -> bool {
1023 self.bit()
1024 }
1025}
1026#[doc = "Possible values of the field `DECAP3`"]
1027#[derive(Clone, Copy, Debug, PartialEq)]
1028pub enum DECAP3R {
1029 #[doc = "The dual edge captures are inactive."]
1030 _0,
1031 #[doc = "The dual edge captures are active."]
1032 _1,
1033}
1034impl DECAP3R {
1035 #[doc = r" Returns `true` if the bit is clear (0)"]
1036 #[inline]
1037 pub fn bit_is_clear(&self) -> bool {
1038 !self.bit()
1039 }
1040 #[doc = r" Returns `true` if the bit is set (1)"]
1041 #[inline]
1042 pub fn bit_is_set(&self) -> bool {
1043 self.bit()
1044 }
1045 #[doc = r" Value of the field as raw bits"]
1046 #[inline]
1047 pub fn bit(&self) -> bool {
1048 match *self {
1049 DECAP3R::_0 => false,
1050 DECAP3R::_1 => true,
1051 }
1052 }
1053 #[allow(missing_docs)]
1054 #[doc(hidden)]
1055 #[inline]
1056 pub fn _from(value: bool) -> DECAP3R {
1057 match value {
1058 false => DECAP3R::_0,
1059 true => DECAP3R::_1,
1060 }
1061 }
1062 #[doc = "Checks if the value of the field is `_0`"]
1063 #[inline]
1064 pub fn is_0(&self) -> bool {
1065 *self == DECAP3R::_0
1066 }
1067 #[doc = "Checks if the value of the field is `_1`"]
1068 #[inline]
1069 pub fn is_1(&self) -> bool {
1070 *self == DECAP3R::_1
1071 }
1072}
1073#[doc = "Possible values of the field `DTEN3`"]
1074#[derive(Clone, Copy, Debug, PartialEq)]
1075pub enum DTEN3R {
1076 #[doc = "The deadtime insertion in this pair of channels is disabled."]
1077 _0,
1078 #[doc = "The deadtime insertion in this pair of channels is enabled."]
1079 _1,
1080}
1081impl DTEN3R {
1082 #[doc = r" Returns `true` if the bit is clear (0)"]
1083 #[inline]
1084 pub fn bit_is_clear(&self) -> bool {
1085 !self.bit()
1086 }
1087 #[doc = r" Returns `true` if the bit is set (1)"]
1088 #[inline]
1089 pub fn bit_is_set(&self) -> bool {
1090 self.bit()
1091 }
1092 #[doc = r" Value of the field as raw bits"]
1093 #[inline]
1094 pub fn bit(&self) -> bool {
1095 match *self {
1096 DTEN3R::_0 => false,
1097 DTEN3R::_1 => true,
1098 }
1099 }
1100 #[allow(missing_docs)]
1101 #[doc(hidden)]
1102 #[inline]
1103 pub fn _from(value: bool) -> DTEN3R {
1104 match value {
1105 false => DTEN3R::_0,
1106 true => DTEN3R::_1,
1107 }
1108 }
1109 #[doc = "Checks if the value of the field is `_0`"]
1110 #[inline]
1111 pub fn is_0(&self) -> bool {
1112 *self == DTEN3R::_0
1113 }
1114 #[doc = "Checks if the value of the field is `_1`"]
1115 #[inline]
1116 pub fn is_1(&self) -> bool {
1117 *self == DTEN3R::_1
1118 }
1119}
1120#[doc = "Possible values of the field `SYNCEN3`"]
1121#[derive(Clone, Copy, Debug, PartialEq)]
1122pub enum SYNCEN3R {
1123 #[doc = "The PWM synchronization in this pair of channels is disabled."]
1124 _0,
1125 #[doc = "The PWM synchronization in this pair of channels is enabled."]
1126 _1,
1127}
1128impl SYNCEN3R {
1129 #[doc = r" Returns `true` if the bit is clear (0)"]
1130 #[inline]
1131 pub fn bit_is_clear(&self) -> bool {
1132 !self.bit()
1133 }
1134 #[doc = r" Returns `true` if the bit is set (1)"]
1135 #[inline]
1136 pub fn bit_is_set(&self) -> bool {
1137 self.bit()
1138 }
1139 #[doc = r" Value of the field as raw bits"]
1140 #[inline]
1141 pub fn bit(&self) -> bool {
1142 match *self {
1143 SYNCEN3R::_0 => false,
1144 SYNCEN3R::_1 => true,
1145 }
1146 }
1147 #[allow(missing_docs)]
1148 #[doc(hidden)]
1149 #[inline]
1150 pub fn _from(value: bool) -> SYNCEN3R {
1151 match value {
1152 false => SYNCEN3R::_0,
1153 true => SYNCEN3R::_1,
1154 }
1155 }
1156 #[doc = "Checks if the value of the field is `_0`"]
1157 #[inline]
1158 pub fn is_0(&self) -> bool {
1159 *self == SYNCEN3R::_0
1160 }
1161 #[doc = "Checks if the value of the field is `_1`"]
1162 #[inline]
1163 pub fn is_1(&self) -> bool {
1164 *self == SYNCEN3R::_1
1165 }
1166}
1167#[doc = "Possible values of the field `FAULTEN3`"]
1168#[derive(Clone, Copy, Debug, PartialEq)]
1169pub enum FAULTEN3R {
1170 #[doc = "The fault control in this pair of channels is disabled."]
1171 _0,
1172 #[doc = "The fault control in this pair of channels is enabled."]
1173 _1,
1174}
1175impl FAULTEN3R {
1176 #[doc = r" Returns `true` if the bit is clear (0)"]
1177 #[inline]
1178 pub fn bit_is_clear(&self) -> bool {
1179 !self.bit()
1180 }
1181 #[doc = r" Returns `true` if the bit is set (1)"]
1182 #[inline]
1183 pub fn bit_is_set(&self) -> bool {
1184 self.bit()
1185 }
1186 #[doc = r" Value of the field as raw bits"]
1187 #[inline]
1188 pub fn bit(&self) -> bool {
1189 match *self {
1190 FAULTEN3R::_0 => false,
1191 FAULTEN3R::_1 => true,
1192 }
1193 }
1194 #[allow(missing_docs)]
1195 #[doc(hidden)]
1196 #[inline]
1197 pub fn _from(value: bool) -> FAULTEN3R {
1198 match value {
1199 false => FAULTEN3R::_0,
1200 true => FAULTEN3R::_1,
1201 }
1202 }
1203 #[doc = "Checks if the value of the field is `_0`"]
1204 #[inline]
1205 pub fn is_0(&self) -> bool {
1206 *self == FAULTEN3R::_0
1207 }
1208 #[doc = "Checks if the value of the field is `_1`"]
1209 #[inline]
1210 pub fn is_1(&self) -> bool {
1211 *self == FAULTEN3R::_1
1212 }
1213}
1214#[doc = r" Value of the field"]
1215pub struct MCOMBINE3R {
1216 bits: bool,
1217}
1218impl MCOMBINE3R {
1219 #[doc = r" Value of the field as raw bits"]
1220 #[inline]
1221 pub fn bit(&self) -> bool {
1222 self.bits
1223 }
1224 #[doc = r" Returns `true` if the bit is clear (0)"]
1225 #[inline]
1226 pub fn bit_is_clear(&self) -> bool {
1227 !self.bit()
1228 }
1229 #[doc = r" Returns `true` if the bit is set (1)"]
1230 #[inline]
1231 pub fn bit_is_set(&self) -> bool {
1232 self.bit()
1233 }
1234}
1235#[doc = r" Proxy"]
1236pub struct _COMBINE0W<'a> {
1237 w: &'a mut W,
1238}
1239impl<'a> _COMBINE0W<'a> {
1240 #[doc = r" Sets the field bit"]
1241 pub fn set_bit(self) -> &'a mut W {
1242 self.bit(true)
1243 }
1244 #[doc = r" Clears the field bit"]
1245 pub fn clear_bit(self) -> &'a mut W {
1246 self.bit(false)
1247 }
1248 #[doc = r" Writes raw bits to the field"]
1249 #[inline]
1250 pub fn bit(self, value: bool) -> &'a mut W {
1251 const MASK: bool = true;
1252 const OFFSET: u8 = 0;
1253 self.w.bits &= !((MASK as u32) << OFFSET);
1254 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1255 self.w
1256 }
1257}
1258#[doc = "Values that can be written to the field `COMP0`"]
1259pub enum COMP0W {
1260 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
1261 _0,
1262 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
1263 _1,
1264}
1265impl COMP0W {
1266 #[allow(missing_docs)]
1267 #[doc(hidden)]
1268 #[inline]
1269 pub fn _bits(&self) -> bool {
1270 match *self {
1271 COMP0W::_0 => false,
1272 COMP0W::_1 => true,
1273 }
1274 }
1275}
1276#[doc = r" Proxy"]
1277pub struct _COMP0W<'a> {
1278 w: &'a mut W,
1279}
1280impl<'a> _COMP0W<'a> {
1281 #[doc = r" Writes `variant` to the field"]
1282 #[inline]
1283 pub fn variant(self, variant: COMP0W) -> &'a mut W {
1284 {
1285 self.bit(variant._bits())
1286 }
1287 }
1288 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
1289 #[inline]
1290 pub fn _0(self) -> &'a mut W {
1291 self.variant(COMP0W::_0)
1292 }
1293 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
1294 #[inline]
1295 pub fn _1(self) -> &'a mut W {
1296 self.variant(COMP0W::_1)
1297 }
1298 #[doc = r" Sets the field bit"]
1299 pub fn set_bit(self) -> &'a mut W {
1300 self.bit(true)
1301 }
1302 #[doc = r" Clears the field bit"]
1303 pub fn clear_bit(self) -> &'a mut W {
1304 self.bit(false)
1305 }
1306 #[doc = r" Writes raw bits to the field"]
1307 #[inline]
1308 pub fn bit(self, value: bool) -> &'a mut W {
1309 const MASK: bool = true;
1310 const OFFSET: u8 = 1;
1311 self.w.bits &= !((MASK as u32) << OFFSET);
1312 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1313 self.w
1314 }
1315}
1316#[doc = r" Proxy"]
1317pub struct _DECAPEN0W<'a> {
1318 w: &'a mut W,
1319}
1320impl<'a> _DECAPEN0W<'a> {
1321 #[doc = r" Sets the field bit"]
1322 pub fn set_bit(self) -> &'a mut W {
1323 self.bit(true)
1324 }
1325 #[doc = r" Clears the field bit"]
1326 pub fn clear_bit(self) -> &'a mut W {
1327 self.bit(false)
1328 }
1329 #[doc = r" Writes raw bits to the field"]
1330 #[inline]
1331 pub fn bit(self, value: bool) -> &'a mut W {
1332 const MASK: bool = true;
1333 const OFFSET: u8 = 2;
1334 self.w.bits &= !((MASK as u32) << OFFSET);
1335 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1336 self.w
1337 }
1338}
1339#[doc = "Values that can be written to the field `DECAP0`"]
1340pub enum DECAP0W {
1341 #[doc = "The dual edge captures are inactive."]
1342 _0,
1343 #[doc = "The dual edge captures are active."]
1344 _1,
1345}
1346impl DECAP0W {
1347 #[allow(missing_docs)]
1348 #[doc(hidden)]
1349 #[inline]
1350 pub fn _bits(&self) -> bool {
1351 match *self {
1352 DECAP0W::_0 => false,
1353 DECAP0W::_1 => true,
1354 }
1355 }
1356}
1357#[doc = r" Proxy"]
1358pub struct _DECAP0W<'a> {
1359 w: &'a mut W,
1360}
1361impl<'a> _DECAP0W<'a> {
1362 #[doc = r" Writes `variant` to the field"]
1363 #[inline]
1364 pub fn variant(self, variant: DECAP0W) -> &'a mut W {
1365 {
1366 self.bit(variant._bits())
1367 }
1368 }
1369 #[doc = "The dual edge captures are inactive."]
1370 #[inline]
1371 pub fn _0(self) -> &'a mut W {
1372 self.variant(DECAP0W::_0)
1373 }
1374 #[doc = "The dual edge captures are active."]
1375 #[inline]
1376 pub fn _1(self) -> &'a mut W {
1377 self.variant(DECAP0W::_1)
1378 }
1379 #[doc = r" Sets the field bit"]
1380 pub fn set_bit(self) -> &'a mut W {
1381 self.bit(true)
1382 }
1383 #[doc = r" Clears the field bit"]
1384 pub fn clear_bit(self) -> &'a mut W {
1385 self.bit(false)
1386 }
1387 #[doc = r" Writes raw bits to the field"]
1388 #[inline]
1389 pub fn bit(self, value: bool) -> &'a mut W {
1390 const MASK: bool = true;
1391 const OFFSET: u8 = 3;
1392 self.w.bits &= !((MASK as u32) << OFFSET);
1393 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1394 self.w
1395 }
1396}
1397#[doc = "Values that can be written to the field `DTEN0`"]
1398pub enum DTEN0W {
1399 #[doc = "The deadtime insertion in this pair of channels is disabled."]
1400 _0,
1401 #[doc = "The deadtime insertion in this pair of channels is enabled."]
1402 _1,
1403}
1404impl DTEN0W {
1405 #[allow(missing_docs)]
1406 #[doc(hidden)]
1407 #[inline]
1408 pub fn _bits(&self) -> bool {
1409 match *self {
1410 DTEN0W::_0 => false,
1411 DTEN0W::_1 => true,
1412 }
1413 }
1414}
1415#[doc = r" Proxy"]
1416pub struct _DTEN0W<'a> {
1417 w: &'a mut W,
1418}
1419impl<'a> _DTEN0W<'a> {
1420 #[doc = r" Writes `variant` to the field"]
1421 #[inline]
1422 pub fn variant(self, variant: DTEN0W) -> &'a mut W {
1423 {
1424 self.bit(variant._bits())
1425 }
1426 }
1427 #[doc = "The deadtime insertion in this pair of channels is disabled."]
1428 #[inline]
1429 pub fn _0(self) -> &'a mut W {
1430 self.variant(DTEN0W::_0)
1431 }
1432 #[doc = "The deadtime insertion in this pair of channels is enabled."]
1433 #[inline]
1434 pub fn _1(self) -> &'a mut W {
1435 self.variant(DTEN0W::_1)
1436 }
1437 #[doc = r" Sets the field bit"]
1438 pub fn set_bit(self) -> &'a mut W {
1439 self.bit(true)
1440 }
1441 #[doc = r" Clears the field bit"]
1442 pub fn clear_bit(self) -> &'a mut W {
1443 self.bit(false)
1444 }
1445 #[doc = r" Writes raw bits to the field"]
1446 #[inline]
1447 pub fn bit(self, value: bool) -> &'a mut W {
1448 const MASK: bool = true;
1449 const OFFSET: u8 = 4;
1450 self.w.bits &= !((MASK as u32) << OFFSET);
1451 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1452 self.w
1453 }
1454}
1455#[doc = "Values that can be written to the field `SYNCEN0`"]
1456pub enum SYNCEN0W {
1457 #[doc = "The PWM synchronization in this pair of channels is disabled."]
1458 _0,
1459 #[doc = "The PWM synchronization in this pair of channels is enabled."]
1460 _1,
1461}
1462impl SYNCEN0W {
1463 #[allow(missing_docs)]
1464 #[doc(hidden)]
1465 #[inline]
1466 pub fn _bits(&self) -> bool {
1467 match *self {
1468 SYNCEN0W::_0 => false,
1469 SYNCEN0W::_1 => true,
1470 }
1471 }
1472}
1473#[doc = r" Proxy"]
1474pub struct _SYNCEN0W<'a> {
1475 w: &'a mut W,
1476}
1477impl<'a> _SYNCEN0W<'a> {
1478 #[doc = r" Writes `variant` to the field"]
1479 #[inline]
1480 pub fn variant(self, variant: SYNCEN0W) -> &'a mut W {
1481 {
1482 self.bit(variant._bits())
1483 }
1484 }
1485 #[doc = "The PWM synchronization in this pair of channels is disabled."]
1486 #[inline]
1487 pub fn _0(self) -> &'a mut W {
1488 self.variant(SYNCEN0W::_0)
1489 }
1490 #[doc = "The PWM synchronization in this pair of channels is enabled."]
1491 #[inline]
1492 pub fn _1(self) -> &'a mut W {
1493 self.variant(SYNCEN0W::_1)
1494 }
1495 #[doc = r" Sets the field bit"]
1496 pub fn set_bit(self) -> &'a mut W {
1497 self.bit(true)
1498 }
1499 #[doc = r" Clears the field bit"]
1500 pub fn clear_bit(self) -> &'a mut W {
1501 self.bit(false)
1502 }
1503 #[doc = r" Writes raw bits to the field"]
1504 #[inline]
1505 pub fn bit(self, value: bool) -> &'a mut W {
1506 const MASK: bool = true;
1507 const OFFSET: u8 = 5;
1508 self.w.bits &= !((MASK as u32) << OFFSET);
1509 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1510 self.w
1511 }
1512}
1513#[doc = "Values that can be written to the field `FAULTEN0`"]
1514pub enum FAULTEN0W {
1515 #[doc = "The fault control in this pair of channels is disabled."]
1516 _0,
1517 #[doc = "The fault control in this pair of channels is enabled."]
1518 _1,
1519}
1520impl FAULTEN0W {
1521 #[allow(missing_docs)]
1522 #[doc(hidden)]
1523 #[inline]
1524 pub fn _bits(&self) -> bool {
1525 match *self {
1526 FAULTEN0W::_0 => false,
1527 FAULTEN0W::_1 => true,
1528 }
1529 }
1530}
1531#[doc = r" Proxy"]
1532pub struct _FAULTEN0W<'a> {
1533 w: &'a mut W,
1534}
1535impl<'a> _FAULTEN0W<'a> {
1536 #[doc = r" Writes `variant` to the field"]
1537 #[inline]
1538 pub fn variant(self, variant: FAULTEN0W) -> &'a mut W {
1539 {
1540 self.bit(variant._bits())
1541 }
1542 }
1543 #[doc = "The fault control in this pair of channels is disabled."]
1544 #[inline]
1545 pub fn _0(self) -> &'a mut W {
1546 self.variant(FAULTEN0W::_0)
1547 }
1548 #[doc = "The fault control in this pair of channels is enabled."]
1549 #[inline]
1550 pub fn _1(self) -> &'a mut W {
1551 self.variant(FAULTEN0W::_1)
1552 }
1553 #[doc = r" Sets the field bit"]
1554 pub fn set_bit(self) -> &'a mut W {
1555 self.bit(true)
1556 }
1557 #[doc = r" Clears the field bit"]
1558 pub fn clear_bit(self) -> &'a mut W {
1559 self.bit(false)
1560 }
1561 #[doc = r" Writes raw bits to the field"]
1562 #[inline]
1563 pub fn bit(self, value: bool) -> &'a mut W {
1564 const MASK: bool = true;
1565 const OFFSET: u8 = 6;
1566 self.w.bits &= !((MASK as u32) << OFFSET);
1567 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1568 self.w
1569 }
1570}
1571#[doc = r" Proxy"]
1572pub struct _MCOMBINE0W<'a> {
1573 w: &'a mut W,
1574}
1575impl<'a> _MCOMBINE0W<'a> {
1576 #[doc = r" Sets the field bit"]
1577 pub fn set_bit(self) -> &'a mut W {
1578 self.bit(true)
1579 }
1580 #[doc = r" Clears the field bit"]
1581 pub fn clear_bit(self) -> &'a mut W {
1582 self.bit(false)
1583 }
1584 #[doc = r" Writes raw bits to the field"]
1585 #[inline]
1586 pub fn bit(self, value: bool) -> &'a mut W {
1587 const MASK: bool = true;
1588 const OFFSET: u8 = 7;
1589 self.w.bits &= !((MASK as u32) << OFFSET);
1590 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1591 self.w
1592 }
1593}
1594#[doc = r" Proxy"]
1595pub struct _COMBINE1W<'a> {
1596 w: &'a mut W,
1597}
1598impl<'a> _COMBINE1W<'a> {
1599 #[doc = r" Sets the field bit"]
1600 pub fn set_bit(self) -> &'a mut W {
1601 self.bit(true)
1602 }
1603 #[doc = r" Clears the field bit"]
1604 pub fn clear_bit(self) -> &'a mut W {
1605 self.bit(false)
1606 }
1607 #[doc = r" Writes raw bits to the field"]
1608 #[inline]
1609 pub fn bit(self, value: bool) -> &'a mut W {
1610 const MASK: bool = true;
1611 const OFFSET: u8 = 8;
1612 self.w.bits &= !((MASK as u32) << OFFSET);
1613 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1614 self.w
1615 }
1616}
1617#[doc = "Values that can be written to the field `COMP1`"]
1618pub enum COMP1W {
1619 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
1620 _0,
1621 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
1622 _1,
1623}
1624impl COMP1W {
1625 #[allow(missing_docs)]
1626 #[doc(hidden)]
1627 #[inline]
1628 pub fn _bits(&self) -> bool {
1629 match *self {
1630 COMP1W::_0 => false,
1631 COMP1W::_1 => true,
1632 }
1633 }
1634}
1635#[doc = r" Proxy"]
1636pub struct _COMP1W<'a> {
1637 w: &'a mut W,
1638}
1639impl<'a> _COMP1W<'a> {
1640 #[doc = r" Writes `variant` to the field"]
1641 #[inline]
1642 pub fn variant(self, variant: COMP1W) -> &'a mut W {
1643 {
1644 self.bit(variant._bits())
1645 }
1646 }
1647 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
1648 #[inline]
1649 pub fn _0(self) -> &'a mut W {
1650 self.variant(COMP1W::_0)
1651 }
1652 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
1653 #[inline]
1654 pub fn _1(self) -> &'a mut W {
1655 self.variant(COMP1W::_1)
1656 }
1657 #[doc = r" Sets the field bit"]
1658 pub fn set_bit(self) -> &'a mut W {
1659 self.bit(true)
1660 }
1661 #[doc = r" Clears the field bit"]
1662 pub fn clear_bit(self) -> &'a mut W {
1663 self.bit(false)
1664 }
1665 #[doc = r" Writes raw bits to the field"]
1666 #[inline]
1667 pub fn bit(self, value: bool) -> &'a mut W {
1668 const MASK: bool = true;
1669 const OFFSET: u8 = 9;
1670 self.w.bits &= !((MASK as u32) << OFFSET);
1671 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1672 self.w
1673 }
1674}
1675#[doc = r" Proxy"]
1676pub struct _DECAPEN1W<'a> {
1677 w: &'a mut W,
1678}
1679impl<'a> _DECAPEN1W<'a> {
1680 #[doc = r" Sets the field bit"]
1681 pub fn set_bit(self) -> &'a mut W {
1682 self.bit(true)
1683 }
1684 #[doc = r" Clears the field bit"]
1685 pub fn clear_bit(self) -> &'a mut W {
1686 self.bit(false)
1687 }
1688 #[doc = r" Writes raw bits to the field"]
1689 #[inline]
1690 pub fn bit(self, value: bool) -> &'a mut W {
1691 const MASK: bool = true;
1692 const OFFSET: u8 = 10;
1693 self.w.bits &= !((MASK as u32) << OFFSET);
1694 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1695 self.w
1696 }
1697}
1698#[doc = "Values that can be written to the field `DECAP1`"]
1699pub enum DECAP1W {
1700 #[doc = "The dual edge captures are inactive."]
1701 _0,
1702 #[doc = "The dual edge captures are active."]
1703 _1,
1704}
1705impl DECAP1W {
1706 #[allow(missing_docs)]
1707 #[doc(hidden)]
1708 #[inline]
1709 pub fn _bits(&self) -> bool {
1710 match *self {
1711 DECAP1W::_0 => false,
1712 DECAP1W::_1 => true,
1713 }
1714 }
1715}
1716#[doc = r" Proxy"]
1717pub struct _DECAP1W<'a> {
1718 w: &'a mut W,
1719}
1720impl<'a> _DECAP1W<'a> {
1721 #[doc = r" Writes `variant` to the field"]
1722 #[inline]
1723 pub fn variant(self, variant: DECAP1W) -> &'a mut W {
1724 {
1725 self.bit(variant._bits())
1726 }
1727 }
1728 #[doc = "The dual edge captures are inactive."]
1729 #[inline]
1730 pub fn _0(self) -> &'a mut W {
1731 self.variant(DECAP1W::_0)
1732 }
1733 #[doc = "The dual edge captures are active."]
1734 #[inline]
1735 pub fn _1(self) -> &'a mut W {
1736 self.variant(DECAP1W::_1)
1737 }
1738 #[doc = r" Sets the field bit"]
1739 pub fn set_bit(self) -> &'a mut W {
1740 self.bit(true)
1741 }
1742 #[doc = r" Clears the field bit"]
1743 pub fn clear_bit(self) -> &'a mut W {
1744 self.bit(false)
1745 }
1746 #[doc = r" Writes raw bits to the field"]
1747 #[inline]
1748 pub fn bit(self, value: bool) -> &'a mut W {
1749 const MASK: bool = true;
1750 const OFFSET: u8 = 11;
1751 self.w.bits &= !((MASK as u32) << OFFSET);
1752 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1753 self.w
1754 }
1755}
1756#[doc = "Values that can be written to the field `DTEN1`"]
1757pub enum DTEN1W {
1758 #[doc = "The deadtime insertion in this pair of channels is disabled."]
1759 _0,
1760 #[doc = "The deadtime insertion in this pair of channels is enabled."]
1761 _1,
1762}
1763impl DTEN1W {
1764 #[allow(missing_docs)]
1765 #[doc(hidden)]
1766 #[inline]
1767 pub fn _bits(&self) -> bool {
1768 match *self {
1769 DTEN1W::_0 => false,
1770 DTEN1W::_1 => true,
1771 }
1772 }
1773}
1774#[doc = r" Proxy"]
1775pub struct _DTEN1W<'a> {
1776 w: &'a mut W,
1777}
1778impl<'a> _DTEN1W<'a> {
1779 #[doc = r" Writes `variant` to the field"]
1780 #[inline]
1781 pub fn variant(self, variant: DTEN1W) -> &'a mut W {
1782 {
1783 self.bit(variant._bits())
1784 }
1785 }
1786 #[doc = "The deadtime insertion in this pair of channels is disabled."]
1787 #[inline]
1788 pub fn _0(self) -> &'a mut W {
1789 self.variant(DTEN1W::_0)
1790 }
1791 #[doc = "The deadtime insertion in this pair of channels is enabled."]
1792 #[inline]
1793 pub fn _1(self) -> &'a mut W {
1794 self.variant(DTEN1W::_1)
1795 }
1796 #[doc = r" Sets the field bit"]
1797 pub fn set_bit(self) -> &'a mut W {
1798 self.bit(true)
1799 }
1800 #[doc = r" Clears the field bit"]
1801 pub fn clear_bit(self) -> &'a mut W {
1802 self.bit(false)
1803 }
1804 #[doc = r" Writes raw bits to the field"]
1805 #[inline]
1806 pub fn bit(self, value: bool) -> &'a mut W {
1807 const MASK: bool = true;
1808 const OFFSET: u8 = 12;
1809 self.w.bits &= !((MASK as u32) << OFFSET);
1810 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1811 self.w
1812 }
1813}
1814#[doc = "Values that can be written to the field `SYNCEN1`"]
1815pub enum SYNCEN1W {
1816 #[doc = "The PWM synchronization in this pair of channels is disabled."]
1817 _0,
1818 #[doc = "The PWM synchronization in this pair of channels is enabled."]
1819 _1,
1820}
1821impl SYNCEN1W {
1822 #[allow(missing_docs)]
1823 #[doc(hidden)]
1824 #[inline]
1825 pub fn _bits(&self) -> bool {
1826 match *self {
1827 SYNCEN1W::_0 => false,
1828 SYNCEN1W::_1 => true,
1829 }
1830 }
1831}
1832#[doc = r" Proxy"]
1833pub struct _SYNCEN1W<'a> {
1834 w: &'a mut W,
1835}
1836impl<'a> _SYNCEN1W<'a> {
1837 #[doc = r" Writes `variant` to the field"]
1838 #[inline]
1839 pub fn variant(self, variant: SYNCEN1W) -> &'a mut W {
1840 {
1841 self.bit(variant._bits())
1842 }
1843 }
1844 #[doc = "The PWM synchronization in this pair of channels is disabled."]
1845 #[inline]
1846 pub fn _0(self) -> &'a mut W {
1847 self.variant(SYNCEN1W::_0)
1848 }
1849 #[doc = "The PWM synchronization in this pair of channels is enabled."]
1850 #[inline]
1851 pub fn _1(self) -> &'a mut W {
1852 self.variant(SYNCEN1W::_1)
1853 }
1854 #[doc = r" Sets the field bit"]
1855 pub fn set_bit(self) -> &'a mut W {
1856 self.bit(true)
1857 }
1858 #[doc = r" Clears the field bit"]
1859 pub fn clear_bit(self) -> &'a mut W {
1860 self.bit(false)
1861 }
1862 #[doc = r" Writes raw bits to the field"]
1863 #[inline]
1864 pub fn bit(self, value: bool) -> &'a mut W {
1865 const MASK: bool = true;
1866 const OFFSET: u8 = 13;
1867 self.w.bits &= !((MASK as u32) << OFFSET);
1868 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1869 self.w
1870 }
1871}
1872#[doc = "Values that can be written to the field `FAULTEN1`"]
1873pub enum FAULTEN1W {
1874 #[doc = "The fault control in this pair of channels is disabled."]
1875 _0,
1876 #[doc = "The fault control in this pair of channels is enabled."]
1877 _1,
1878}
1879impl FAULTEN1W {
1880 #[allow(missing_docs)]
1881 #[doc(hidden)]
1882 #[inline]
1883 pub fn _bits(&self) -> bool {
1884 match *self {
1885 FAULTEN1W::_0 => false,
1886 FAULTEN1W::_1 => true,
1887 }
1888 }
1889}
1890#[doc = r" Proxy"]
1891pub struct _FAULTEN1W<'a> {
1892 w: &'a mut W,
1893}
1894impl<'a> _FAULTEN1W<'a> {
1895 #[doc = r" Writes `variant` to the field"]
1896 #[inline]
1897 pub fn variant(self, variant: FAULTEN1W) -> &'a mut W {
1898 {
1899 self.bit(variant._bits())
1900 }
1901 }
1902 #[doc = "The fault control in this pair of channels is disabled."]
1903 #[inline]
1904 pub fn _0(self) -> &'a mut W {
1905 self.variant(FAULTEN1W::_0)
1906 }
1907 #[doc = "The fault control in this pair of channels is enabled."]
1908 #[inline]
1909 pub fn _1(self) -> &'a mut W {
1910 self.variant(FAULTEN1W::_1)
1911 }
1912 #[doc = r" Sets the field bit"]
1913 pub fn set_bit(self) -> &'a mut W {
1914 self.bit(true)
1915 }
1916 #[doc = r" Clears the field bit"]
1917 pub fn clear_bit(self) -> &'a mut W {
1918 self.bit(false)
1919 }
1920 #[doc = r" Writes raw bits to the field"]
1921 #[inline]
1922 pub fn bit(self, value: bool) -> &'a mut W {
1923 const MASK: bool = true;
1924 const OFFSET: u8 = 14;
1925 self.w.bits &= !((MASK as u32) << OFFSET);
1926 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1927 self.w
1928 }
1929}
1930#[doc = r" Proxy"]
1931pub struct _MCOMBINE1W<'a> {
1932 w: &'a mut W,
1933}
1934impl<'a> _MCOMBINE1W<'a> {
1935 #[doc = r" Sets the field bit"]
1936 pub fn set_bit(self) -> &'a mut W {
1937 self.bit(true)
1938 }
1939 #[doc = r" Clears the field bit"]
1940 pub fn clear_bit(self) -> &'a mut W {
1941 self.bit(false)
1942 }
1943 #[doc = r" Writes raw bits to the field"]
1944 #[inline]
1945 pub fn bit(self, value: bool) -> &'a mut W {
1946 const MASK: bool = true;
1947 const OFFSET: u8 = 15;
1948 self.w.bits &= !((MASK as u32) << OFFSET);
1949 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1950 self.w
1951 }
1952}
1953#[doc = r" Proxy"]
1954pub struct _COMBINE2W<'a> {
1955 w: &'a mut W,
1956}
1957impl<'a> _COMBINE2W<'a> {
1958 #[doc = r" Sets the field bit"]
1959 pub fn set_bit(self) -> &'a mut W {
1960 self.bit(true)
1961 }
1962 #[doc = r" Clears the field bit"]
1963 pub fn clear_bit(self) -> &'a mut W {
1964 self.bit(false)
1965 }
1966 #[doc = r" Writes raw bits to the field"]
1967 #[inline]
1968 pub fn bit(self, value: bool) -> &'a mut W {
1969 const MASK: bool = true;
1970 const OFFSET: u8 = 16;
1971 self.w.bits &= !((MASK as u32) << OFFSET);
1972 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1973 self.w
1974 }
1975}
1976#[doc = "Values that can be written to the field `COMP2`"]
1977pub enum COMP2W {
1978 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
1979 _0,
1980 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
1981 _1,
1982}
1983impl COMP2W {
1984 #[allow(missing_docs)]
1985 #[doc(hidden)]
1986 #[inline]
1987 pub fn _bits(&self) -> bool {
1988 match *self {
1989 COMP2W::_0 => false,
1990 COMP2W::_1 => true,
1991 }
1992 }
1993}
1994#[doc = r" Proxy"]
1995pub struct _COMP2W<'a> {
1996 w: &'a mut W,
1997}
1998impl<'a> _COMP2W<'a> {
1999 #[doc = r" Writes `variant` to the field"]
2000 #[inline]
2001 pub fn variant(self, variant: COMP2W) -> &'a mut W {
2002 {
2003 self.bit(variant._bits())
2004 }
2005 }
2006 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
2007 #[inline]
2008 pub fn _0(self) -> &'a mut W {
2009 self.variant(COMP2W::_0)
2010 }
2011 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
2012 #[inline]
2013 pub fn _1(self) -> &'a mut W {
2014 self.variant(COMP2W::_1)
2015 }
2016 #[doc = r" Sets the field bit"]
2017 pub fn set_bit(self) -> &'a mut W {
2018 self.bit(true)
2019 }
2020 #[doc = r" Clears the field bit"]
2021 pub fn clear_bit(self) -> &'a mut W {
2022 self.bit(false)
2023 }
2024 #[doc = r" Writes raw bits to the field"]
2025 #[inline]
2026 pub fn bit(self, value: bool) -> &'a mut W {
2027 const MASK: bool = true;
2028 const OFFSET: u8 = 17;
2029 self.w.bits &= !((MASK as u32) << OFFSET);
2030 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2031 self.w
2032 }
2033}
2034#[doc = r" Proxy"]
2035pub struct _DECAPEN2W<'a> {
2036 w: &'a mut W,
2037}
2038impl<'a> _DECAPEN2W<'a> {
2039 #[doc = r" Sets the field bit"]
2040 pub fn set_bit(self) -> &'a mut W {
2041 self.bit(true)
2042 }
2043 #[doc = r" Clears the field bit"]
2044 pub fn clear_bit(self) -> &'a mut W {
2045 self.bit(false)
2046 }
2047 #[doc = r" Writes raw bits to the field"]
2048 #[inline]
2049 pub fn bit(self, value: bool) -> &'a mut W {
2050 const MASK: bool = true;
2051 const OFFSET: u8 = 18;
2052 self.w.bits &= !((MASK as u32) << OFFSET);
2053 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2054 self.w
2055 }
2056}
2057#[doc = "Values that can be written to the field `DECAP2`"]
2058pub enum DECAP2W {
2059 #[doc = "The dual edge captures are inactive."]
2060 _0,
2061 #[doc = "The dual edge captures are active."]
2062 _1,
2063}
2064impl DECAP2W {
2065 #[allow(missing_docs)]
2066 #[doc(hidden)]
2067 #[inline]
2068 pub fn _bits(&self) -> bool {
2069 match *self {
2070 DECAP2W::_0 => false,
2071 DECAP2W::_1 => true,
2072 }
2073 }
2074}
2075#[doc = r" Proxy"]
2076pub struct _DECAP2W<'a> {
2077 w: &'a mut W,
2078}
2079impl<'a> _DECAP2W<'a> {
2080 #[doc = r" Writes `variant` to the field"]
2081 #[inline]
2082 pub fn variant(self, variant: DECAP2W) -> &'a mut W {
2083 {
2084 self.bit(variant._bits())
2085 }
2086 }
2087 #[doc = "The dual edge captures are inactive."]
2088 #[inline]
2089 pub fn _0(self) -> &'a mut W {
2090 self.variant(DECAP2W::_0)
2091 }
2092 #[doc = "The dual edge captures are active."]
2093 #[inline]
2094 pub fn _1(self) -> &'a mut W {
2095 self.variant(DECAP2W::_1)
2096 }
2097 #[doc = r" Sets the field bit"]
2098 pub fn set_bit(self) -> &'a mut W {
2099 self.bit(true)
2100 }
2101 #[doc = r" Clears the field bit"]
2102 pub fn clear_bit(self) -> &'a mut W {
2103 self.bit(false)
2104 }
2105 #[doc = r" Writes raw bits to the field"]
2106 #[inline]
2107 pub fn bit(self, value: bool) -> &'a mut W {
2108 const MASK: bool = true;
2109 const OFFSET: u8 = 19;
2110 self.w.bits &= !((MASK as u32) << OFFSET);
2111 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2112 self.w
2113 }
2114}
2115#[doc = "Values that can be written to the field `DTEN2`"]
2116pub enum DTEN2W {
2117 #[doc = "The deadtime insertion in this pair of channels is disabled."]
2118 _0,
2119 #[doc = "The deadtime insertion in this pair of channels is enabled."]
2120 _1,
2121}
2122impl DTEN2W {
2123 #[allow(missing_docs)]
2124 #[doc(hidden)]
2125 #[inline]
2126 pub fn _bits(&self) -> bool {
2127 match *self {
2128 DTEN2W::_0 => false,
2129 DTEN2W::_1 => true,
2130 }
2131 }
2132}
2133#[doc = r" Proxy"]
2134pub struct _DTEN2W<'a> {
2135 w: &'a mut W,
2136}
2137impl<'a> _DTEN2W<'a> {
2138 #[doc = r" Writes `variant` to the field"]
2139 #[inline]
2140 pub fn variant(self, variant: DTEN2W) -> &'a mut W {
2141 {
2142 self.bit(variant._bits())
2143 }
2144 }
2145 #[doc = "The deadtime insertion in this pair of channels is disabled."]
2146 #[inline]
2147 pub fn _0(self) -> &'a mut W {
2148 self.variant(DTEN2W::_0)
2149 }
2150 #[doc = "The deadtime insertion in this pair of channels is enabled."]
2151 #[inline]
2152 pub fn _1(self) -> &'a mut W {
2153 self.variant(DTEN2W::_1)
2154 }
2155 #[doc = r" Sets the field bit"]
2156 pub fn set_bit(self) -> &'a mut W {
2157 self.bit(true)
2158 }
2159 #[doc = r" Clears the field bit"]
2160 pub fn clear_bit(self) -> &'a mut W {
2161 self.bit(false)
2162 }
2163 #[doc = r" Writes raw bits to the field"]
2164 #[inline]
2165 pub fn bit(self, value: bool) -> &'a mut W {
2166 const MASK: bool = true;
2167 const OFFSET: u8 = 20;
2168 self.w.bits &= !((MASK as u32) << OFFSET);
2169 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2170 self.w
2171 }
2172}
2173#[doc = "Values that can be written to the field `SYNCEN2`"]
2174pub enum SYNCEN2W {
2175 #[doc = "The PWM synchronization in this pair of channels is disabled."]
2176 _0,
2177 #[doc = "The PWM synchronization in this pair of channels is enabled."]
2178 _1,
2179}
2180impl SYNCEN2W {
2181 #[allow(missing_docs)]
2182 #[doc(hidden)]
2183 #[inline]
2184 pub fn _bits(&self) -> bool {
2185 match *self {
2186 SYNCEN2W::_0 => false,
2187 SYNCEN2W::_1 => true,
2188 }
2189 }
2190}
2191#[doc = r" Proxy"]
2192pub struct _SYNCEN2W<'a> {
2193 w: &'a mut W,
2194}
2195impl<'a> _SYNCEN2W<'a> {
2196 #[doc = r" Writes `variant` to the field"]
2197 #[inline]
2198 pub fn variant(self, variant: SYNCEN2W) -> &'a mut W {
2199 {
2200 self.bit(variant._bits())
2201 }
2202 }
2203 #[doc = "The PWM synchronization in this pair of channels is disabled."]
2204 #[inline]
2205 pub fn _0(self) -> &'a mut W {
2206 self.variant(SYNCEN2W::_0)
2207 }
2208 #[doc = "The PWM synchronization in this pair of channels is enabled."]
2209 #[inline]
2210 pub fn _1(self) -> &'a mut W {
2211 self.variant(SYNCEN2W::_1)
2212 }
2213 #[doc = r" Sets the field bit"]
2214 pub fn set_bit(self) -> &'a mut W {
2215 self.bit(true)
2216 }
2217 #[doc = r" Clears the field bit"]
2218 pub fn clear_bit(self) -> &'a mut W {
2219 self.bit(false)
2220 }
2221 #[doc = r" Writes raw bits to the field"]
2222 #[inline]
2223 pub fn bit(self, value: bool) -> &'a mut W {
2224 const MASK: bool = true;
2225 const OFFSET: u8 = 21;
2226 self.w.bits &= !((MASK as u32) << OFFSET);
2227 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2228 self.w
2229 }
2230}
2231#[doc = "Values that can be written to the field `FAULTEN2`"]
2232pub enum FAULTEN2W {
2233 #[doc = "The fault control in this pair of channels is disabled."]
2234 _0,
2235 #[doc = "The fault control in this pair of channels is enabled."]
2236 _1,
2237}
2238impl FAULTEN2W {
2239 #[allow(missing_docs)]
2240 #[doc(hidden)]
2241 #[inline]
2242 pub fn _bits(&self) -> bool {
2243 match *self {
2244 FAULTEN2W::_0 => false,
2245 FAULTEN2W::_1 => true,
2246 }
2247 }
2248}
2249#[doc = r" Proxy"]
2250pub struct _FAULTEN2W<'a> {
2251 w: &'a mut W,
2252}
2253impl<'a> _FAULTEN2W<'a> {
2254 #[doc = r" Writes `variant` to the field"]
2255 #[inline]
2256 pub fn variant(self, variant: FAULTEN2W) -> &'a mut W {
2257 {
2258 self.bit(variant._bits())
2259 }
2260 }
2261 #[doc = "The fault control in this pair of channels is disabled."]
2262 #[inline]
2263 pub fn _0(self) -> &'a mut W {
2264 self.variant(FAULTEN2W::_0)
2265 }
2266 #[doc = "The fault control in this pair of channels is enabled."]
2267 #[inline]
2268 pub fn _1(self) -> &'a mut W {
2269 self.variant(FAULTEN2W::_1)
2270 }
2271 #[doc = r" Sets the field bit"]
2272 pub fn set_bit(self) -> &'a mut W {
2273 self.bit(true)
2274 }
2275 #[doc = r" Clears the field bit"]
2276 pub fn clear_bit(self) -> &'a mut W {
2277 self.bit(false)
2278 }
2279 #[doc = r" Writes raw bits to the field"]
2280 #[inline]
2281 pub fn bit(self, value: bool) -> &'a mut W {
2282 const MASK: bool = true;
2283 const OFFSET: u8 = 22;
2284 self.w.bits &= !((MASK as u32) << OFFSET);
2285 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2286 self.w
2287 }
2288}
2289#[doc = r" Proxy"]
2290pub struct _MCOMBINE2W<'a> {
2291 w: &'a mut W,
2292}
2293impl<'a> _MCOMBINE2W<'a> {
2294 #[doc = r" Sets the field bit"]
2295 pub fn set_bit(self) -> &'a mut W {
2296 self.bit(true)
2297 }
2298 #[doc = r" Clears the field bit"]
2299 pub fn clear_bit(self) -> &'a mut W {
2300 self.bit(false)
2301 }
2302 #[doc = r" Writes raw bits to the field"]
2303 #[inline]
2304 pub fn bit(self, value: bool) -> &'a mut W {
2305 const MASK: bool = true;
2306 const OFFSET: u8 = 23;
2307 self.w.bits &= !((MASK as u32) << OFFSET);
2308 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2309 self.w
2310 }
2311}
2312#[doc = r" Proxy"]
2313pub struct _COMBINE3W<'a> {
2314 w: &'a mut W,
2315}
2316impl<'a> _COMBINE3W<'a> {
2317 #[doc = r" Sets the field bit"]
2318 pub fn set_bit(self) -> &'a mut W {
2319 self.bit(true)
2320 }
2321 #[doc = r" Clears the field bit"]
2322 pub fn clear_bit(self) -> &'a mut W {
2323 self.bit(false)
2324 }
2325 #[doc = r" Writes raw bits to the field"]
2326 #[inline]
2327 pub fn bit(self, value: bool) -> &'a mut W {
2328 const MASK: bool = true;
2329 const OFFSET: u8 = 24;
2330 self.w.bits &= !((MASK as u32) << OFFSET);
2331 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2332 self.w
2333 }
2334}
2335#[doc = "Values that can be written to the field `COMP3`"]
2336pub enum COMP3W {
2337 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
2338 _0,
2339 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
2340 _1,
2341}
2342impl COMP3W {
2343 #[allow(missing_docs)]
2344 #[doc(hidden)]
2345 #[inline]
2346 pub fn _bits(&self) -> bool {
2347 match *self {
2348 COMP3W::_0 => false,
2349 COMP3W::_1 => true,
2350 }
2351 }
2352}
2353#[doc = r" Proxy"]
2354pub struct _COMP3W<'a> {
2355 w: &'a mut W,
2356}
2357impl<'a> _COMP3W<'a> {
2358 #[doc = r" Writes `variant` to the field"]
2359 #[inline]
2360 pub fn variant(self, variant: COMP3W) -> &'a mut W {
2361 {
2362 self.bit(variant._bits())
2363 }
2364 }
2365 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
2366 #[inline]
2367 pub fn _0(self) -> &'a mut W {
2368 self.variant(COMP3W::_0)
2369 }
2370 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
2371 #[inline]
2372 pub fn _1(self) -> &'a mut W {
2373 self.variant(COMP3W::_1)
2374 }
2375 #[doc = r" Sets the field bit"]
2376 pub fn set_bit(self) -> &'a mut W {
2377 self.bit(true)
2378 }
2379 #[doc = r" Clears the field bit"]
2380 pub fn clear_bit(self) -> &'a mut W {
2381 self.bit(false)
2382 }
2383 #[doc = r" Writes raw bits to the field"]
2384 #[inline]
2385 pub fn bit(self, value: bool) -> &'a mut W {
2386 const MASK: bool = true;
2387 const OFFSET: u8 = 25;
2388 self.w.bits &= !((MASK as u32) << OFFSET);
2389 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2390 self.w
2391 }
2392}
2393#[doc = r" Proxy"]
2394pub struct _DECAPEN3W<'a> {
2395 w: &'a mut W,
2396}
2397impl<'a> _DECAPEN3W<'a> {
2398 #[doc = r" Sets the field bit"]
2399 pub fn set_bit(self) -> &'a mut W {
2400 self.bit(true)
2401 }
2402 #[doc = r" Clears the field bit"]
2403 pub fn clear_bit(self) -> &'a mut W {
2404 self.bit(false)
2405 }
2406 #[doc = r" Writes raw bits to the field"]
2407 #[inline]
2408 pub fn bit(self, value: bool) -> &'a mut W {
2409 const MASK: bool = true;
2410 const OFFSET: u8 = 26;
2411 self.w.bits &= !((MASK as u32) << OFFSET);
2412 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2413 self.w
2414 }
2415}
2416#[doc = "Values that can be written to the field `DECAP3`"]
2417pub enum DECAP3W {
2418 #[doc = "The dual edge captures are inactive."]
2419 _0,
2420 #[doc = "The dual edge captures are active."]
2421 _1,
2422}
2423impl DECAP3W {
2424 #[allow(missing_docs)]
2425 #[doc(hidden)]
2426 #[inline]
2427 pub fn _bits(&self) -> bool {
2428 match *self {
2429 DECAP3W::_0 => false,
2430 DECAP3W::_1 => true,
2431 }
2432 }
2433}
2434#[doc = r" Proxy"]
2435pub struct _DECAP3W<'a> {
2436 w: &'a mut W,
2437}
2438impl<'a> _DECAP3W<'a> {
2439 #[doc = r" Writes `variant` to the field"]
2440 #[inline]
2441 pub fn variant(self, variant: DECAP3W) -> &'a mut W {
2442 {
2443 self.bit(variant._bits())
2444 }
2445 }
2446 #[doc = "The dual edge captures are inactive."]
2447 #[inline]
2448 pub fn _0(self) -> &'a mut W {
2449 self.variant(DECAP3W::_0)
2450 }
2451 #[doc = "The dual edge captures are active."]
2452 #[inline]
2453 pub fn _1(self) -> &'a mut W {
2454 self.variant(DECAP3W::_1)
2455 }
2456 #[doc = r" Sets the field bit"]
2457 pub fn set_bit(self) -> &'a mut W {
2458 self.bit(true)
2459 }
2460 #[doc = r" Clears the field bit"]
2461 pub fn clear_bit(self) -> &'a mut W {
2462 self.bit(false)
2463 }
2464 #[doc = r" Writes raw bits to the field"]
2465 #[inline]
2466 pub fn bit(self, value: bool) -> &'a mut W {
2467 const MASK: bool = true;
2468 const OFFSET: u8 = 27;
2469 self.w.bits &= !((MASK as u32) << OFFSET);
2470 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2471 self.w
2472 }
2473}
2474#[doc = "Values that can be written to the field `DTEN3`"]
2475pub enum DTEN3W {
2476 #[doc = "The deadtime insertion in this pair of channels is disabled."]
2477 _0,
2478 #[doc = "The deadtime insertion in this pair of channels is enabled."]
2479 _1,
2480}
2481impl DTEN3W {
2482 #[allow(missing_docs)]
2483 #[doc(hidden)]
2484 #[inline]
2485 pub fn _bits(&self) -> bool {
2486 match *self {
2487 DTEN3W::_0 => false,
2488 DTEN3W::_1 => true,
2489 }
2490 }
2491}
2492#[doc = r" Proxy"]
2493pub struct _DTEN3W<'a> {
2494 w: &'a mut W,
2495}
2496impl<'a> _DTEN3W<'a> {
2497 #[doc = r" Writes `variant` to the field"]
2498 #[inline]
2499 pub fn variant(self, variant: DTEN3W) -> &'a mut W {
2500 {
2501 self.bit(variant._bits())
2502 }
2503 }
2504 #[doc = "The deadtime insertion in this pair of channels is disabled."]
2505 #[inline]
2506 pub fn _0(self) -> &'a mut W {
2507 self.variant(DTEN3W::_0)
2508 }
2509 #[doc = "The deadtime insertion in this pair of channels is enabled."]
2510 #[inline]
2511 pub fn _1(self) -> &'a mut W {
2512 self.variant(DTEN3W::_1)
2513 }
2514 #[doc = r" Sets the field bit"]
2515 pub fn set_bit(self) -> &'a mut W {
2516 self.bit(true)
2517 }
2518 #[doc = r" Clears the field bit"]
2519 pub fn clear_bit(self) -> &'a mut W {
2520 self.bit(false)
2521 }
2522 #[doc = r" Writes raw bits to the field"]
2523 #[inline]
2524 pub fn bit(self, value: bool) -> &'a mut W {
2525 const MASK: bool = true;
2526 const OFFSET: u8 = 28;
2527 self.w.bits &= !((MASK as u32) << OFFSET);
2528 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2529 self.w
2530 }
2531}
2532#[doc = "Values that can be written to the field `SYNCEN3`"]
2533pub enum SYNCEN3W {
2534 #[doc = "The PWM synchronization in this pair of channels is disabled."]
2535 _0,
2536 #[doc = "The PWM synchronization in this pair of channels is enabled."]
2537 _1,
2538}
2539impl SYNCEN3W {
2540 #[allow(missing_docs)]
2541 #[doc(hidden)]
2542 #[inline]
2543 pub fn _bits(&self) -> bool {
2544 match *self {
2545 SYNCEN3W::_0 => false,
2546 SYNCEN3W::_1 => true,
2547 }
2548 }
2549}
2550#[doc = r" Proxy"]
2551pub struct _SYNCEN3W<'a> {
2552 w: &'a mut W,
2553}
2554impl<'a> _SYNCEN3W<'a> {
2555 #[doc = r" Writes `variant` to the field"]
2556 #[inline]
2557 pub fn variant(self, variant: SYNCEN3W) -> &'a mut W {
2558 {
2559 self.bit(variant._bits())
2560 }
2561 }
2562 #[doc = "The PWM synchronization in this pair of channels is disabled."]
2563 #[inline]
2564 pub fn _0(self) -> &'a mut W {
2565 self.variant(SYNCEN3W::_0)
2566 }
2567 #[doc = "The PWM synchronization in this pair of channels is enabled."]
2568 #[inline]
2569 pub fn _1(self) -> &'a mut W {
2570 self.variant(SYNCEN3W::_1)
2571 }
2572 #[doc = r" Sets the field bit"]
2573 pub fn set_bit(self) -> &'a mut W {
2574 self.bit(true)
2575 }
2576 #[doc = r" Clears the field bit"]
2577 pub fn clear_bit(self) -> &'a mut W {
2578 self.bit(false)
2579 }
2580 #[doc = r" Writes raw bits to the field"]
2581 #[inline]
2582 pub fn bit(self, value: bool) -> &'a mut W {
2583 const MASK: bool = true;
2584 const OFFSET: u8 = 29;
2585 self.w.bits &= !((MASK as u32) << OFFSET);
2586 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2587 self.w
2588 }
2589}
2590#[doc = "Values that can be written to the field `FAULTEN3`"]
2591pub enum FAULTEN3W {
2592 #[doc = "The fault control in this pair of channels is disabled."]
2593 _0,
2594 #[doc = "The fault control in this pair of channels is enabled."]
2595 _1,
2596}
2597impl FAULTEN3W {
2598 #[allow(missing_docs)]
2599 #[doc(hidden)]
2600 #[inline]
2601 pub fn _bits(&self) -> bool {
2602 match *self {
2603 FAULTEN3W::_0 => false,
2604 FAULTEN3W::_1 => true,
2605 }
2606 }
2607}
2608#[doc = r" Proxy"]
2609pub struct _FAULTEN3W<'a> {
2610 w: &'a mut W,
2611}
2612impl<'a> _FAULTEN3W<'a> {
2613 #[doc = r" Writes `variant` to the field"]
2614 #[inline]
2615 pub fn variant(self, variant: FAULTEN3W) -> &'a mut W {
2616 {
2617 self.bit(variant._bits())
2618 }
2619 }
2620 #[doc = "The fault control in this pair of channels is disabled."]
2621 #[inline]
2622 pub fn _0(self) -> &'a mut W {
2623 self.variant(FAULTEN3W::_0)
2624 }
2625 #[doc = "The fault control in this pair of channels is enabled."]
2626 #[inline]
2627 pub fn _1(self) -> &'a mut W {
2628 self.variant(FAULTEN3W::_1)
2629 }
2630 #[doc = r" Sets the field bit"]
2631 pub fn set_bit(self) -> &'a mut W {
2632 self.bit(true)
2633 }
2634 #[doc = r" Clears the field bit"]
2635 pub fn clear_bit(self) -> &'a mut W {
2636 self.bit(false)
2637 }
2638 #[doc = r" Writes raw bits to the field"]
2639 #[inline]
2640 pub fn bit(self, value: bool) -> &'a mut W {
2641 const MASK: bool = true;
2642 const OFFSET: u8 = 30;
2643 self.w.bits &= !((MASK as u32) << OFFSET);
2644 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2645 self.w
2646 }
2647}
2648#[doc = r" Proxy"]
2649pub struct _MCOMBINE3W<'a> {
2650 w: &'a mut W,
2651}
2652impl<'a> _MCOMBINE3W<'a> {
2653 #[doc = r" Sets the field bit"]
2654 pub fn set_bit(self) -> &'a mut W {
2655 self.bit(true)
2656 }
2657 #[doc = r" Clears the field bit"]
2658 pub fn clear_bit(self) -> &'a mut W {
2659 self.bit(false)
2660 }
2661 #[doc = r" Writes raw bits to the field"]
2662 #[inline]
2663 pub fn bit(self, value: bool) -> &'a mut W {
2664 const MASK: bool = true;
2665 const OFFSET: u8 = 31;
2666 self.w.bits &= !((MASK as u32) << OFFSET);
2667 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2668 self.w
2669 }
2670}
2671impl R {
2672 #[doc = r" Value of the register as raw bits"]
2673 #[inline]
2674 pub fn bits(&self) -> u32 {
2675 self.bits
2676 }
2677 #[doc = "Bit 0 - Combine Channels For n = 0"]
2678 #[inline]
2679 pub fn combine0(&self) -> COMBINE0R {
2680 let bits = {
2681 const MASK: bool = true;
2682 const OFFSET: u8 = 0;
2683 ((self.bits >> OFFSET) & MASK as u32) != 0
2684 };
2685 COMBINE0R { bits }
2686 }
2687 #[doc = "Bit 1 - Complement Of Channel (n) For n = 0"]
2688 #[inline]
2689 pub fn comp0(&self) -> COMP0R {
2690 COMP0R::_from({
2691 const MASK: bool = true;
2692 const OFFSET: u8 = 1;
2693 ((self.bits >> OFFSET) & MASK as u32) != 0
2694 })
2695 }
2696 #[doc = "Bit 2 - Dual Edge Capture Mode Enable For n = 0"]
2697 #[inline]
2698 pub fn decapen0(&self) -> DECAPEN0R {
2699 let bits = {
2700 const MASK: bool = true;
2701 const OFFSET: u8 = 2;
2702 ((self.bits >> OFFSET) & MASK as u32) != 0
2703 };
2704 DECAPEN0R { bits }
2705 }
2706 #[doc = "Bit 3 - Dual Edge Capture Mode Captures For n = 0"]
2707 #[inline]
2708 pub fn decap0(&self) -> DECAP0R {
2709 DECAP0R::_from({
2710 const MASK: bool = true;
2711 const OFFSET: u8 = 3;
2712 ((self.bits >> OFFSET) & MASK as u32) != 0
2713 })
2714 }
2715 #[doc = "Bit 4 - Deadtime Enable For n = 0"]
2716 #[inline]
2717 pub fn dten0(&self) -> DTEN0R {
2718 DTEN0R::_from({
2719 const MASK: bool = true;
2720 const OFFSET: u8 = 4;
2721 ((self.bits >> OFFSET) & MASK as u32) != 0
2722 })
2723 }
2724 #[doc = "Bit 5 - Synchronization Enable For n = 0"]
2725 #[inline]
2726 pub fn syncen0(&self) -> SYNCEN0R {
2727 SYNCEN0R::_from({
2728 const MASK: bool = true;
2729 const OFFSET: u8 = 5;
2730 ((self.bits >> OFFSET) & MASK as u32) != 0
2731 })
2732 }
2733 #[doc = "Bit 6 - Fault Control Enable For n = 0"]
2734 #[inline]
2735 pub fn faulten0(&self) -> FAULTEN0R {
2736 FAULTEN0R::_from({
2737 const MASK: bool = true;
2738 const OFFSET: u8 = 6;
2739 ((self.bits >> OFFSET) & MASK as u32) != 0
2740 })
2741 }
2742 #[doc = "Bit 7 - Modified Combine Mode For n = 0"]
2743 #[inline]
2744 pub fn mcombine0(&self) -> MCOMBINE0R {
2745 let bits = {
2746 const MASK: bool = true;
2747 const OFFSET: u8 = 7;
2748 ((self.bits >> OFFSET) & MASK as u32) != 0
2749 };
2750 MCOMBINE0R { bits }
2751 }
2752 #[doc = "Bit 8 - Combine Channels For n = 2"]
2753 #[inline]
2754 pub fn combine1(&self) -> COMBINE1R {
2755 let bits = {
2756 const MASK: bool = true;
2757 const OFFSET: u8 = 8;
2758 ((self.bits >> OFFSET) & MASK as u32) != 0
2759 };
2760 COMBINE1R { bits }
2761 }
2762 #[doc = "Bit 9 - Complement Of Channel (n) For n = 2"]
2763 #[inline]
2764 pub fn comp1(&self) -> COMP1R {
2765 COMP1R::_from({
2766 const MASK: bool = true;
2767 const OFFSET: u8 = 9;
2768 ((self.bits >> OFFSET) & MASK as u32) != 0
2769 })
2770 }
2771 #[doc = "Bit 10 - Dual Edge Capture Mode Enable For n = 2"]
2772 #[inline]
2773 pub fn decapen1(&self) -> DECAPEN1R {
2774 let bits = {
2775 const MASK: bool = true;
2776 const OFFSET: u8 = 10;
2777 ((self.bits >> OFFSET) & MASK as u32) != 0
2778 };
2779 DECAPEN1R { bits }
2780 }
2781 #[doc = "Bit 11 - Dual Edge Capture Mode Captures For n = 2"]
2782 #[inline]
2783 pub fn decap1(&self) -> DECAP1R {
2784 DECAP1R::_from({
2785 const MASK: bool = true;
2786 const OFFSET: u8 = 11;
2787 ((self.bits >> OFFSET) & MASK as u32) != 0
2788 })
2789 }
2790 #[doc = "Bit 12 - Deadtime Enable For n = 2"]
2791 #[inline]
2792 pub fn dten1(&self) -> DTEN1R {
2793 DTEN1R::_from({
2794 const MASK: bool = true;
2795 const OFFSET: u8 = 12;
2796 ((self.bits >> OFFSET) & MASK as u32) != 0
2797 })
2798 }
2799 #[doc = "Bit 13 - Synchronization Enable For n = 2"]
2800 #[inline]
2801 pub fn syncen1(&self) -> SYNCEN1R {
2802 SYNCEN1R::_from({
2803 const MASK: bool = true;
2804 const OFFSET: u8 = 13;
2805 ((self.bits >> OFFSET) & MASK as u32) != 0
2806 })
2807 }
2808 #[doc = "Bit 14 - Fault Control Enable For n = 2"]
2809 #[inline]
2810 pub fn faulten1(&self) -> FAULTEN1R {
2811 FAULTEN1R::_from({
2812 const MASK: bool = true;
2813 const OFFSET: u8 = 14;
2814 ((self.bits >> OFFSET) & MASK as u32) != 0
2815 })
2816 }
2817 #[doc = "Bit 15 - Modified Combine Mode For n = 2"]
2818 #[inline]
2819 pub fn mcombine1(&self) -> MCOMBINE1R {
2820 let bits = {
2821 const MASK: bool = true;
2822 const OFFSET: u8 = 15;
2823 ((self.bits >> OFFSET) & MASK as u32) != 0
2824 };
2825 MCOMBINE1R { bits }
2826 }
2827 #[doc = "Bit 16 - Combine Channels For n = 4"]
2828 #[inline]
2829 pub fn combine2(&self) -> COMBINE2R {
2830 let bits = {
2831 const MASK: bool = true;
2832 const OFFSET: u8 = 16;
2833 ((self.bits >> OFFSET) & MASK as u32) != 0
2834 };
2835 COMBINE2R { bits }
2836 }
2837 #[doc = "Bit 17 - Complement Of Channel (n) For n = 4"]
2838 #[inline]
2839 pub fn comp2(&self) -> COMP2R {
2840 COMP2R::_from({
2841 const MASK: bool = true;
2842 const OFFSET: u8 = 17;
2843 ((self.bits >> OFFSET) & MASK as u32) != 0
2844 })
2845 }
2846 #[doc = "Bit 18 - Dual Edge Capture Mode Enable For n = 4"]
2847 #[inline]
2848 pub fn decapen2(&self) -> DECAPEN2R {
2849 let bits = {
2850 const MASK: bool = true;
2851 const OFFSET: u8 = 18;
2852 ((self.bits >> OFFSET) & MASK as u32) != 0
2853 };
2854 DECAPEN2R { bits }
2855 }
2856 #[doc = "Bit 19 - Dual Edge Capture Mode Captures For n = 4"]
2857 #[inline]
2858 pub fn decap2(&self) -> DECAP2R {
2859 DECAP2R::_from({
2860 const MASK: bool = true;
2861 const OFFSET: u8 = 19;
2862 ((self.bits >> OFFSET) & MASK as u32) != 0
2863 })
2864 }
2865 #[doc = "Bit 20 - Deadtime Enable For n = 4"]
2866 #[inline]
2867 pub fn dten2(&self) -> DTEN2R {
2868 DTEN2R::_from({
2869 const MASK: bool = true;
2870 const OFFSET: u8 = 20;
2871 ((self.bits >> OFFSET) & MASK as u32) != 0
2872 })
2873 }
2874 #[doc = "Bit 21 - Synchronization Enable For n = 4"]
2875 #[inline]
2876 pub fn syncen2(&self) -> SYNCEN2R {
2877 SYNCEN2R::_from({
2878 const MASK: bool = true;
2879 const OFFSET: u8 = 21;
2880 ((self.bits >> OFFSET) & MASK as u32) != 0
2881 })
2882 }
2883 #[doc = "Bit 22 - Fault Control Enable For n = 4"]
2884 #[inline]
2885 pub fn faulten2(&self) -> FAULTEN2R {
2886 FAULTEN2R::_from({
2887 const MASK: bool = true;
2888 const OFFSET: u8 = 22;
2889 ((self.bits >> OFFSET) & MASK as u32) != 0
2890 })
2891 }
2892 #[doc = "Bit 23 - Modified Combine Mode For n = 4"]
2893 #[inline]
2894 pub fn mcombine2(&self) -> MCOMBINE2R {
2895 let bits = {
2896 const MASK: bool = true;
2897 const OFFSET: u8 = 23;
2898 ((self.bits >> OFFSET) & MASK as u32) != 0
2899 };
2900 MCOMBINE2R { bits }
2901 }
2902 #[doc = "Bit 24 - Combine Channels For n = 6"]
2903 #[inline]
2904 pub fn combine3(&self) -> COMBINE3R {
2905 let bits = {
2906 const MASK: bool = true;
2907 const OFFSET: u8 = 24;
2908 ((self.bits >> OFFSET) & MASK as u32) != 0
2909 };
2910 COMBINE3R { bits }
2911 }
2912 #[doc = "Bit 25 - Complement Of Channel (n) for n = 6"]
2913 #[inline]
2914 pub fn comp3(&self) -> COMP3R {
2915 COMP3R::_from({
2916 const MASK: bool = true;
2917 const OFFSET: u8 = 25;
2918 ((self.bits >> OFFSET) & MASK as u32) != 0
2919 })
2920 }
2921 #[doc = "Bit 26 - Dual Edge Capture Mode Enable For n = 6"]
2922 #[inline]
2923 pub fn decapen3(&self) -> DECAPEN3R {
2924 let bits = {
2925 const MASK: bool = true;
2926 const OFFSET: u8 = 26;
2927 ((self.bits >> OFFSET) & MASK as u32) != 0
2928 };
2929 DECAPEN3R { bits }
2930 }
2931 #[doc = "Bit 27 - Dual Edge Capture Mode Captures For n = 6"]
2932 #[inline]
2933 pub fn decap3(&self) -> DECAP3R {
2934 DECAP3R::_from({
2935 const MASK: bool = true;
2936 const OFFSET: u8 = 27;
2937 ((self.bits >> OFFSET) & MASK as u32) != 0
2938 })
2939 }
2940 #[doc = "Bit 28 - Deadtime Enable For n = 6"]
2941 #[inline]
2942 pub fn dten3(&self) -> DTEN3R {
2943 DTEN3R::_from({
2944 const MASK: bool = true;
2945 const OFFSET: u8 = 28;
2946 ((self.bits >> OFFSET) & MASK as u32) != 0
2947 })
2948 }
2949 #[doc = "Bit 29 - Synchronization Enable For n = 6"]
2950 #[inline]
2951 pub fn syncen3(&self) -> SYNCEN3R {
2952 SYNCEN3R::_from({
2953 const MASK: bool = true;
2954 const OFFSET: u8 = 29;
2955 ((self.bits >> OFFSET) & MASK as u32) != 0
2956 })
2957 }
2958 #[doc = "Bit 30 - Fault Control Enable For n = 6"]
2959 #[inline]
2960 pub fn faulten3(&self) -> FAULTEN3R {
2961 FAULTEN3R::_from({
2962 const MASK: bool = true;
2963 const OFFSET: u8 = 30;
2964 ((self.bits >> OFFSET) & MASK as u32) != 0
2965 })
2966 }
2967 #[doc = "Bit 31 - Modified Combine Mode For n = 6"]
2968 #[inline]
2969 pub fn mcombine3(&self) -> MCOMBINE3R {
2970 let bits = {
2971 const MASK: bool = true;
2972 const OFFSET: u8 = 31;
2973 ((self.bits >> OFFSET) & MASK as u32) != 0
2974 };
2975 MCOMBINE3R { bits }
2976 }
2977}
2978impl W {
2979 #[doc = r" Reset value of the register"]
2980 #[inline]
2981 pub fn reset_value() -> W {
2982 W { bits: 0 }
2983 }
2984 #[doc = r" Writes raw bits to the register"]
2985 #[inline]
2986 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2987 self.bits = bits;
2988 self
2989 }
2990 #[doc = "Bit 0 - Combine Channels For n = 0"]
2991 #[inline]
2992 pub fn combine0(&mut self) -> _COMBINE0W {
2993 _COMBINE0W { w: self }
2994 }
2995 #[doc = "Bit 1 - Complement Of Channel (n) For n = 0"]
2996 #[inline]
2997 pub fn comp0(&mut self) -> _COMP0W {
2998 _COMP0W { w: self }
2999 }
3000 #[doc = "Bit 2 - Dual Edge Capture Mode Enable For n = 0"]
3001 #[inline]
3002 pub fn decapen0(&mut self) -> _DECAPEN0W {
3003 _DECAPEN0W { w: self }
3004 }
3005 #[doc = "Bit 3 - Dual Edge Capture Mode Captures For n = 0"]
3006 #[inline]
3007 pub fn decap0(&mut self) -> _DECAP0W {
3008 _DECAP0W { w: self }
3009 }
3010 #[doc = "Bit 4 - Deadtime Enable For n = 0"]
3011 #[inline]
3012 pub fn dten0(&mut self) -> _DTEN0W {
3013 _DTEN0W { w: self }
3014 }
3015 #[doc = "Bit 5 - Synchronization Enable For n = 0"]
3016 #[inline]
3017 pub fn syncen0(&mut self) -> _SYNCEN0W {
3018 _SYNCEN0W { w: self }
3019 }
3020 #[doc = "Bit 6 - Fault Control Enable For n = 0"]
3021 #[inline]
3022 pub fn faulten0(&mut self) -> _FAULTEN0W {
3023 _FAULTEN0W { w: self }
3024 }
3025 #[doc = "Bit 7 - Modified Combine Mode For n = 0"]
3026 #[inline]
3027 pub fn mcombine0(&mut self) -> _MCOMBINE0W {
3028 _MCOMBINE0W { w: self }
3029 }
3030 #[doc = "Bit 8 - Combine Channels For n = 2"]
3031 #[inline]
3032 pub fn combine1(&mut self) -> _COMBINE1W {
3033 _COMBINE1W { w: self }
3034 }
3035 #[doc = "Bit 9 - Complement Of Channel (n) For n = 2"]
3036 #[inline]
3037 pub fn comp1(&mut self) -> _COMP1W {
3038 _COMP1W { w: self }
3039 }
3040 #[doc = "Bit 10 - Dual Edge Capture Mode Enable For n = 2"]
3041 #[inline]
3042 pub fn decapen1(&mut self) -> _DECAPEN1W {
3043 _DECAPEN1W { w: self }
3044 }
3045 #[doc = "Bit 11 - Dual Edge Capture Mode Captures For n = 2"]
3046 #[inline]
3047 pub fn decap1(&mut self) -> _DECAP1W {
3048 _DECAP1W { w: self }
3049 }
3050 #[doc = "Bit 12 - Deadtime Enable For n = 2"]
3051 #[inline]
3052 pub fn dten1(&mut self) -> _DTEN1W {
3053 _DTEN1W { w: self }
3054 }
3055 #[doc = "Bit 13 - Synchronization Enable For n = 2"]
3056 #[inline]
3057 pub fn syncen1(&mut self) -> _SYNCEN1W {
3058 _SYNCEN1W { w: self }
3059 }
3060 #[doc = "Bit 14 - Fault Control Enable For n = 2"]
3061 #[inline]
3062 pub fn faulten1(&mut self) -> _FAULTEN1W {
3063 _FAULTEN1W { w: self }
3064 }
3065 #[doc = "Bit 15 - Modified Combine Mode For n = 2"]
3066 #[inline]
3067 pub fn mcombine1(&mut self) -> _MCOMBINE1W {
3068 _MCOMBINE1W { w: self }
3069 }
3070 #[doc = "Bit 16 - Combine Channels For n = 4"]
3071 #[inline]
3072 pub fn combine2(&mut self) -> _COMBINE2W {
3073 _COMBINE2W { w: self }
3074 }
3075 #[doc = "Bit 17 - Complement Of Channel (n) For n = 4"]
3076 #[inline]
3077 pub fn comp2(&mut self) -> _COMP2W {
3078 _COMP2W { w: self }
3079 }
3080 #[doc = "Bit 18 - Dual Edge Capture Mode Enable For n = 4"]
3081 #[inline]
3082 pub fn decapen2(&mut self) -> _DECAPEN2W {
3083 _DECAPEN2W { w: self }
3084 }
3085 #[doc = "Bit 19 - Dual Edge Capture Mode Captures For n = 4"]
3086 #[inline]
3087 pub fn decap2(&mut self) -> _DECAP2W {
3088 _DECAP2W { w: self }
3089 }
3090 #[doc = "Bit 20 - Deadtime Enable For n = 4"]
3091 #[inline]
3092 pub fn dten2(&mut self) -> _DTEN2W {
3093 _DTEN2W { w: self }
3094 }
3095 #[doc = "Bit 21 - Synchronization Enable For n = 4"]
3096 #[inline]
3097 pub fn syncen2(&mut self) -> _SYNCEN2W {
3098 _SYNCEN2W { w: self }
3099 }
3100 #[doc = "Bit 22 - Fault Control Enable For n = 4"]
3101 #[inline]
3102 pub fn faulten2(&mut self) -> _FAULTEN2W {
3103 _FAULTEN2W { w: self }
3104 }
3105 #[doc = "Bit 23 - Modified Combine Mode For n = 4"]
3106 #[inline]
3107 pub fn mcombine2(&mut self) -> _MCOMBINE2W {
3108 _MCOMBINE2W { w: self }
3109 }
3110 #[doc = "Bit 24 - Combine Channels For n = 6"]
3111 #[inline]
3112 pub fn combine3(&mut self) -> _COMBINE3W {
3113 _COMBINE3W { w: self }
3114 }
3115 #[doc = "Bit 25 - Complement Of Channel (n) for n = 6"]
3116 #[inline]
3117 pub fn comp3(&mut self) -> _COMP3W {
3118 _COMP3W { w: self }
3119 }
3120 #[doc = "Bit 26 - Dual Edge Capture Mode Enable For n = 6"]
3121 #[inline]
3122 pub fn decapen3(&mut self) -> _DECAPEN3W {
3123 _DECAPEN3W { w: self }
3124 }
3125 #[doc = "Bit 27 - Dual Edge Capture Mode Captures For n = 6"]
3126 #[inline]
3127 pub fn decap3(&mut self) -> _DECAP3W {
3128 _DECAP3W { w: self }
3129 }
3130 #[doc = "Bit 28 - Deadtime Enable For n = 6"]
3131 #[inline]
3132 pub fn dten3(&mut self) -> _DTEN3W {
3133 _DTEN3W { w: self }
3134 }
3135 #[doc = "Bit 29 - Synchronization Enable For n = 6"]
3136 #[inline]
3137 pub fn syncen3(&mut self) -> _SYNCEN3W {
3138 _SYNCEN3W { w: self }
3139 }
3140 #[doc = "Bit 30 - Fault Control Enable For n = 6"]
3141 #[inline]
3142 pub fn faulten3(&mut self) -> _FAULTEN3W {
3143 _FAULTEN3W { w: self }
3144 }
3145 #[doc = "Bit 31 - Modified Combine Mode For n = 6"]
3146 #[inline]
3147 pub fn mcombine3(&mut self) -> _MCOMBINE3W {
3148 _MCOMBINE3W { w: self }
3149 }
3150}