s32k142w_pac/trgmux/
flexio.rs

1#[doc = "Register `FLEXIO` reader"]
2pub struct R(crate::R<FLEXIO_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FLEXIO_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FLEXIO_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FLEXIO_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FLEXIO` writer"]
17pub struct W(crate::W<FLEXIO_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FLEXIO_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FLEXIO_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FLEXIO_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SEL0` reader - Trigger MUX Input 0 Source Select"]
38pub struct SEL0_R(crate::FieldReader<u8, u8>);
39impl SEL0_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u8) -> Self {
42        SEL0_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for SEL0_R {
46    type Target = crate::FieldReader<u8, u8>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `SEL0` writer - Trigger MUX Input 0 Source Select"]
53pub struct SEL0_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> SEL0_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u8) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f);
61        self.w
62    }
63}
64#[doc = "Field `SEL1` reader - Trigger MUX Input 1 Source Select"]
65pub struct SEL1_R(crate::FieldReader<u8, u8>);
66impl SEL1_R {
67    #[inline(always)]
68    pub(crate) fn new(bits: u8) -> Self {
69        SEL1_R(crate::FieldReader::new(bits))
70    }
71}
72impl core::ops::Deref for SEL1_R {
73    type Target = crate::FieldReader<u8, u8>;
74    #[inline(always)]
75    fn deref(&self) -> &Self::Target {
76        &self.0
77    }
78}
79#[doc = "Field `SEL1` writer - Trigger MUX Input 1 Source Select"]
80pub struct SEL1_W<'a> {
81    w: &'a mut W,
82}
83impl<'a> SEL1_W<'a> {
84    #[doc = r"Writes raw bits to the field"]
85    #[inline(always)]
86    pub unsafe fn bits(self, value: u8) -> &'a mut W {
87        self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8);
88        self.w
89    }
90}
91#[doc = "Field `SEL2` reader - Trigger MUX Input 2 Source Select"]
92pub struct SEL2_R(crate::FieldReader<u8, u8>);
93impl SEL2_R {
94    #[inline(always)]
95    pub(crate) fn new(bits: u8) -> Self {
96        SEL2_R(crate::FieldReader::new(bits))
97    }
98}
99impl core::ops::Deref for SEL2_R {
100    type Target = crate::FieldReader<u8, u8>;
101    #[inline(always)]
102    fn deref(&self) -> &Self::Target {
103        &self.0
104    }
105}
106#[doc = "Field `SEL2` writer - Trigger MUX Input 2 Source Select"]
107pub struct SEL2_W<'a> {
108    w: &'a mut W,
109}
110impl<'a> SEL2_W<'a> {
111    #[doc = r"Writes raw bits to the field"]
112    #[inline(always)]
113    pub unsafe fn bits(self, value: u8) -> &'a mut W {
114        self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16);
115        self.w
116    }
117}
118#[doc = "Field `SEL3` reader - Trigger MUX Input 3 Source Select"]
119pub struct SEL3_R(crate::FieldReader<u8, u8>);
120impl SEL3_R {
121    #[inline(always)]
122    pub(crate) fn new(bits: u8) -> Self {
123        SEL3_R(crate::FieldReader::new(bits))
124    }
125}
126impl core::ops::Deref for SEL3_R {
127    type Target = crate::FieldReader<u8, u8>;
128    #[inline(always)]
129    fn deref(&self) -> &Self::Target {
130        &self.0
131    }
132}
133#[doc = "Field `SEL3` writer - Trigger MUX Input 3 Source Select"]
134pub struct SEL3_W<'a> {
135    w: &'a mut W,
136}
137impl<'a> SEL3_W<'a> {
138    #[doc = r"Writes raw bits to the field"]
139    #[inline(always)]
140    pub unsafe fn bits(self, value: u8) -> &'a mut W {
141        self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24);
142        self.w
143    }
144}
145#[doc = "TRGMUX register lock.\n\nValue on reset: 0"]
146#[derive(Clone, Copy, Debug, PartialEq)]
147pub enum LK_A {
148    #[doc = "0: Register can be written."]
149    UNLOCKED = 0,
150    #[doc = "1: Register cannot be written until the next system Reset."]
151    LOCKED = 1,
152}
153impl From<LK_A> for bool {
154    #[inline(always)]
155    fn from(variant: LK_A) -> Self {
156        variant as u8 != 0
157    }
158}
159#[doc = "Field `LK` reader - TRGMUX register lock."]
160pub struct LK_R(crate::FieldReader<bool, LK_A>);
161impl LK_R {
162    #[inline(always)]
163    pub(crate) fn new(bits: bool) -> Self {
164        LK_R(crate::FieldReader::new(bits))
165    }
166    #[doc = r"Get enumerated values variant"]
167    #[inline(always)]
168    pub fn variant(&self) -> LK_A {
169        match self.bits {
170            false => LK_A::UNLOCKED,
171            true => LK_A::LOCKED,
172        }
173    }
174    #[doc = "Checks if the value of the field is `UNLOCKED`"]
175    #[inline(always)]
176    pub fn is_unlocked(&self) -> bool {
177        **self == LK_A::UNLOCKED
178    }
179    #[doc = "Checks if the value of the field is `LOCKED`"]
180    #[inline(always)]
181    pub fn is_locked(&self) -> bool {
182        **self == LK_A::LOCKED
183    }
184}
185impl core::ops::Deref for LK_R {
186    type Target = crate::FieldReader<bool, LK_A>;
187    #[inline(always)]
188    fn deref(&self) -> &Self::Target {
189        &self.0
190    }
191}
192#[doc = "Field `LK` writer - TRGMUX register lock."]
193pub struct LK_W<'a> {
194    w: &'a mut W,
195}
196impl<'a> LK_W<'a> {
197    #[doc = r"Writes `variant` to the field"]
198    #[inline(always)]
199    pub fn variant(self, variant: LK_A) -> &'a mut W {
200        self.bit(variant.into())
201    }
202    #[doc = "Register can be written."]
203    #[inline(always)]
204    pub fn unlocked(self) -> &'a mut W {
205        self.variant(LK_A::UNLOCKED)
206    }
207    #[doc = "Register cannot be written until the next system Reset."]
208    #[inline(always)]
209    pub fn locked(self) -> &'a mut W {
210        self.variant(LK_A::LOCKED)
211    }
212    #[doc = r"Sets the field bit"]
213    #[inline(always)]
214    pub fn set_bit(self) -> &'a mut W {
215        self.bit(true)
216    }
217    #[doc = r"Clears the field bit"]
218    #[inline(always)]
219    pub fn clear_bit(self) -> &'a mut W {
220        self.bit(false)
221    }
222    #[doc = r"Writes raw bits to the field"]
223    #[inline(always)]
224    pub fn bit(self, value: bool) -> &'a mut W {
225        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
226        self.w
227    }
228}
229impl R {
230    #[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
231    #[inline(always)]
232    pub fn sel0(&self) -> SEL0_R {
233        SEL0_R::new((self.bits & 0x3f) as u8)
234    }
235    #[doc = "Bits 8:13 - Trigger MUX Input 1 Source Select"]
236    #[inline(always)]
237    pub fn sel1(&self) -> SEL1_R {
238        SEL1_R::new(((self.bits >> 8) & 0x3f) as u8)
239    }
240    #[doc = "Bits 16:21 - Trigger MUX Input 2 Source Select"]
241    #[inline(always)]
242    pub fn sel2(&self) -> SEL2_R {
243        SEL2_R::new(((self.bits >> 16) & 0x3f) as u8)
244    }
245    #[doc = "Bits 24:29 - Trigger MUX Input 3 Source Select"]
246    #[inline(always)]
247    pub fn sel3(&self) -> SEL3_R {
248        SEL3_R::new(((self.bits >> 24) & 0x3f) as u8)
249    }
250    #[doc = "Bit 31 - TRGMUX register lock."]
251    #[inline(always)]
252    pub fn lk(&self) -> LK_R {
253        LK_R::new(((self.bits >> 31) & 0x01) != 0)
254    }
255}
256impl W {
257    #[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
258    #[inline(always)]
259    pub fn sel0(&mut self) -> SEL0_W {
260        SEL0_W { w: self }
261    }
262    #[doc = "Bits 8:13 - Trigger MUX Input 1 Source Select"]
263    #[inline(always)]
264    pub fn sel1(&mut self) -> SEL1_W {
265        SEL1_W { w: self }
266    }
267    #[doc = "Bits 16:21 - Trigger MUX Input 2 Source Select"]
268    #[inline(always)]
269    pub fn sel2(&mut self) -> SEL2_W {
270        SEL2_W { w: self }
271    }
272    #[doc = "Bits 24:29 - Trigger MUX Input 3 Source Select"]
273    #[inline(always)]
274    pub fn sel3(&mut self) -> SEL3_W {
275        SEL3_W { w: self }
276    }
277    #[doc = "Bit 31 - TRGMUX register lock."]
278    #[inline(always)]
279    pub fn lk(&mut self) -> LK_W {
280        LK_W { w: self }
281    }
282    #[doc = "Writes raw bits to the register."]
283    #[inline(always)]
284    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
285        self.0.bits(bits);
286        self
287    }
288}
289#[doc = "TRGMUX FLEXIO Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexio](index.html) module"]
290pub struct FLEXIO_SPEC;
291impl crate::RegisterSpec for FLEXIO_SPEC {
292    type Ux = u32;
293}
294#[doc = "`read()` method returns [flexio::R](R) reader structure"]
295impl crate::Readable for FLEXIO_SPEC {
296    type Reader = R;
297}
298#[doc = "`write(|w| ..)` method takes [flexio::W](W) writer structure"]
299impl crate::Writable for FLEXIO_SPEC {
300    type Writer = W;
301}
302#[doc = "`reset()` method sets FLEXIO to value 0"]
303impl crate::Resettable for FLEXIO_SPEC {
304    #[inline(always)]
305    fn reset_value() -> Self::Ux {
306        0
307    }
308}
s32k142w_pac/trgmux/flexio.rs

s32k142w_pac/trgmux/
flexio.rs
