1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x04],
5 #[doc = "0x04 - Chip Control register"]
6 pub chipctl: crate::Reg<chipctl::CHIPCTL_SPEC>,
7 _reserved1: [u8; 0x04],
8 #[doc = "0x0c - FTM Option Register 0"]
9 pub ftmopt0: crate::Reg<ftmopt0::FTMOPT0_SPEC>,
10 #[doc = "0x10 - LPO Clock Select Register"]
11 pub lpoclks: crate::Reg<lpoclks::LPOCLKS_SPEC>,
12 _reserved3: [u8; 0x04],
13 #[doc = "0x18 - ADC Options Register"]
14 pub adcopt: crate::Reg<adcopt::ADCOPT_SPEC>,
15 #[doc = "0x1c - FTM Option Register 1"]
16 pub ftmopt1: crate::Reg<ftmopt1::FTMOPT1_SPEC>,
17 #[doc = "0x20 - Miscellaneous control register 0"]
18 pub misctrl0: crate::Reg<misctrl0::MISCTRL0_SPEC>,
19 #[doc = "0x24 - System Device Identification Register"]
20 pub sdid: crate::Reg<sdid::SDID_SPEC>,
21 _reserved7: [u8; 0x18],
22 #[doc = "0x40 - Platform Clock Gating Control Register"]
23 pub platcgc: crate::Reg<platcgc::PLATCGC_SPEC>,
24 _reserved8: [u8; 0x08],
25 #[doc = "0x4c - Flash Configuration Register 1"]
26 pub fcfg1: crate::Reg<fcfg1::FCFG1_SPEC>,
27 _reserved9: [u8; 0x04],
28 #[doc = "0x54 - Unique Identification Register High"]
29 pub uidh: crate::Reg<uidh::UIDH_SPEC>,
30 #[doc = "0x58 - Unique Identification Register Mid-High"]
31 pub uidmh: crate::Reg<uidmh::UIDMH_SPEC>,
32 #[doc = "0x5c - Unique Identification Register Mid Low"]
33 pub uidml: crate::Reg<uidml::UIDML_SPEC>,
34 #[doc = "0x60 - Unique Identification Register Low"]
35 pub uidl: crate::Reg<uidl::UIDL_SPEC>,
36 _reserved13: [u8; 0x04],
37 #[doc = "0x68 - System Clock Divider Register 4"]
38 pub clkdiv4: crate::Reg<clkdiv4::CLKDIV4_SPEC>,
39 #[doc = "0x6c - Miscellaneous Control register 1"]
40 pub misctrl1: crate::Reg<misctrl1::MISCTRL1_SPEC>,
41}
42#[doc = "CHIPCTL register accessor: an alias for `Reg<CHIPCTL_SPEC>`"]
43pub type CHIPCTL = crate::Reg<chipctl::CHIPCTL_SPEC>;
44#[doc = "Chip Control register"]
45pub mod chipctl;
46#[doc = "FTMOPT0 register accessor: an alias for `Reg<FTMOPT0_SPEC>`"]
47pub type FTMOPT0 = crate::Reg<ftmopt0::FTMOPT0_SPEC>;
48#[doc = "FTM Option Register 0"]
49pub mod ftmopt0;
50#[doc = "LPOCLKS register accessor: an alias for `Reg<LPOCLKS_SPEC>`"]
51pub type LPOCLKS = crate::Reg<lpoclks::LPOCLKS_SPEC>;
52#[doc = "LPO Clock Select Register"]
53pub mod lpoclks;
54#[doc = "ADCOPT register accessor: an alias for `Reg<ADCOPT_SPEC>`"]
55pub type ADCOPT = crate::Reg<adcopt::ADCOPT_SPEC>;
56#[doc = "ADC Options Register"]
57pub mod adcopt;
58#[doc = "FTMOPT1 register accessor: an alias for `Reg<FTMOPT1_SPEC>`"]
59pub type FTMOPT1 = crate::Reg<ftmopt1::FTMOPT1_SPEC>;
60#[doc = "FTM Option Register 1"]
61pub mod ftmopt1;
62#[doc = "MISCTRL0 register accessor: an alias for `Reg<MISCTRL0_SPEC>`"]
63pub type MISCTRL0 = crate::Reg<misctrl0::MISCTRL0_SPEC>;
64#[doc = "Miscellaneous control register 0"]
65pub mod misctrl0;
66#[doc = "SDID register accessor: an alias for `Reg<SDID_SPEC>`"]
67pub type SDID = crate::Reg<sdid::SDID_SPEC>;
68#[doc = "System Device Identification Register"]
69pub mod sdid;
70#[doc = "PLATCGC register accessor: an alias for `Reg<PLATCGC_SPEC>`"]
71pub type PLATCGC = crate::Reg<platcgc::PLATCGC_SPEC>;
72#[doc = "Platform Clock Gating Control Register"]
73pub mod platcgc;
74#[doc = "FCFG1 register accessor: an alias for `Reg<FCFG1_SPEC>`"]
75pub type FCFG1 = crate::Reg<fcfg1::FCFG1_SPEC>;
76#[doc = "Flash Configuration Register 1"]
77pub mod fcfg1;
78#[doc = "UIDH register accessor: an alias for `Reg<UIDH_SPEC>`"]
79pub type UIDH = crate::Reg<uidh::UIDH_SPEC>;
80#[doc = "Unique Identification Register High"]
81pub mod uidh;
82#[doc = "UIDMH register accessor: an alias for `Reg<UIDMH_SPEC>`"]
83pub type UIDMH = crate::Reg<uidmh::UIDMH_SPEC>;
84#[doc = "Unique Identification Register Mid-High"]
85pub mod uidmh;
86#[doc = "UIDML register accessor: an alias for `Reg<UIDML_SPEC>`"]
87pub type UIDML = crate::Reg<uidml::UIDML_SPEC>;
88#[doc = "Unique Identification Register Mid Low"]
89pub mod uidml;
90#[doc = "UIDL register accessor: an alias for `Reg<UIDL_SPEC>`"]
91pub type UIDL = crate::Reg<uidl::UIDL_SPEC>;
92#[doc = "Unique Identification Register Low"]
93pub mod uidl;
94#[doc = "CLKDIV4 register accessor: an alias for `Reg<CLKDIV4_SPEC>`"]
95pub type CLKDIV4 = crate::Reg<clkdiv4::CLKDIV4_SPEC>;
96#[doc = "System Clock Divider Register 4"]
97pub mod clkdiv4;
98#[doc = "MISCTRL1 register accessor: an alias for `Reg<MISCTRL1_SPEC>`"]
99pub type MISCTRL1 = crate::Reg<misctrl1::MISCTRL1_SPEC>;
100#[doc = "Miscellaneous Control register 1"]
101pub mod misctrl1;