1#[doc = "Register `CFG1` reader"]
2pub struct R(crate::R<CFG1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CFG1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CFG1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CFG1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CFG1` writer"]
17pub struct W(crate::W<CFG1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CFG1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CFG1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CFG1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Input Clock Select\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum ADICLK_A {
41 #[doc = "0: Alternate clock 1 (ADC_ALTCLK1)"]
42 _00 = 0,
43 #[doc = "1: Alternate clock 2 (ADC_ALTCLK2)"]
44 _01 = 1,
45 #[doc = "2: Alternate clock 3 (ADC_ALTCLK3)"]
46 _10 = 2,
47 #[doc = "3: Alternate clock 4 (ADC_ALTCLK4)"]
48 _11 = 3,
49}
50impl From<ADICLK_A> for u8 {
51 #[inline(always)]
52 fn from(variant: ADICLK_A) -> Self {
53 variant as _
54 }
55}
56#[doc = "Field `ADICLK` reader - Input Clock Select"]
57pub struct ADICLK_R(crate::FieldReader<u8, ADICLK_A>);
58impl ADICLK_R {
59 #[inline(always)]
60 pub(crate) fn new(bits: u8) -> Self {
61 ADICLK_R(crate::FieldReader::new(bits))
62 }
63 #[doc = r"Get enumerated values variant"]
64 #[inline(always)]
65 pub fn variant(&self) -> ADICLK_A {
66 match self.bits {
67 0 => ADICLK_A::_00,
68 1 => ADICLK_A::_01,
69 2 => ADICLK_A::_10,
70 3 => ADICLK_A::_11,
71 _ => unreachable!(),
72 }
73 }
74 #[doc = "Checks if the value of the field is `_00`"]
75 #[inline(always)]
76 pub fn is_00(&self) -> bool {
77 **self == ADICLK_A::_00
78 }
79 #[doc = "Checks if the value of the field is `_01`"]
80 #[inline(always)]
81 pub fn is_01(&self) -> bool {
82 **self == ADICLK_A::_01
83 }
84 #[doc = "Checks if the value of the field is `_10`"]
85 #[inline(always)]
86 pub fn is_10(&self) -> bool {
87 **self == ADICLK_A::_10
88 }
89 #[doc = "Checks if the value of the field is `_11`"]
90 #[inline(always)]
91 pub fn is_11(&self) -> bool {
92 **self == ADICLK_A::_11
93 }
94}
95impl core::ops::Deref for ADICLK_R {
96 type Target = crate::FieldReader<u8, ADICLK_A>;
97 #[inline(always)]
98 fn deref(&self) -> &Self::Target {
99 &self.0
100 }
101}
102#[doc = "Field `ADICLK` writer - Input Clock Select"]
103pub struct ADICLK_W<'a> {
104 w: &'a mut W,
105}
106impl<'a> ADICLK_W<'a> {
107 #[doc = r"Writes `variant` to the field"]
108 #[inline(always)]
109 pub fn variant(self, variant: ADICLK_A) -> &'a mut W {
110 self.bits(variant.into())
111 }
112 #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
113 #[inline(always)]
114 pub fn _00(self) -> &'a mut W {
115 self.variant(ADICLK_A::_00)
116 }
117 #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
118 #[inline(always)]
119 pub fn _01(self) -> &'a mut W {
120 self.variant(ADICLK_A::_01)
121 }
122 #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
123 #[inline(always)]
124 pub fn _10(self) -> &'a mut W {
125 self.variant(ADICLK_A::_10)
126 }
127 #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
128 #[inline(always)]
129 pub fn _11(self) -> &'a mut W {
130 self.variant(ADICLK_A::_11)
131 }
132 #[doc = r"Writes raw bits to the field"]
133 #[inline(always)]
134 pub fn bits(self, value: u8) -> &'a mut W {
135 self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
136 self.w
137 }
138}
139#[doc = "Conversion mode selection\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141#[repr(u8)]
142pub enum MODE_A {
143 #[doc = "0: 8-bit conversion."]
144 _00 = 0,
145 #[doc = "1: 12-bit conversion."]
146 _01 = 1,
147 #[doc = "2: 10-bit conversion."]
148 _10 = 2,
149}
150impl From<MODE_A> for u8 {
151 #[inline(always)]
152 fn from(variant: MODE_A) -> Self {
153 variant as _
154 }
155}
156#[doc = "Field `MODE` reader - Conversion mode selection"]
157pub struct MODE_R(crate::FieldReader<u8, MODE_A>);
158impl MODE_R {
159 #[inline(always)]
160 pub(crate) fn new(bits: u8) -> Self {
161 MODE_R(crate::FieldReader::new(bits))
162 }
163 #[doc = r"Get enumerated values variant"]
164 #[inline(always)]
165 pub fn variant(&self) -> Option<MODE_A> {
166 match self.bits {
167 0 => Some(MODE_A::_00),
168 1 => Some(MODE_A::_01),
169 2 => Some(MODE_A::_10),
170 _ => None,
171 }
172 }
173 #[doc = "Checks if the value of the field is `_00`"]
174 #[inline(always)]
175 pub fn is_00(&self) -> bool {
176 **self == MODE_A::_00
177 }
178 #[doc = "Checks if the value of the field is `_01`"]
179 #[inline(always)]
180 pub fn is_01(&self) -> bool {
181 **self == MODE_A::_01
182 }
183 #[doc = "Checks if the value of the field is `_10`"]
184 #[inline(always)]
185 pub fn is_10(&self) -> bool {
186 **self == MODE_A::_10
187 }
188}
189impl core::ops::Deref for MODE_R {
190 type Target = crate::FieldReader<u8, MODE_A>;
191 #[inline(always)]
192 fn deref(&self) -> &Self::Target {
193 &self.0
194 }
195}
196#[doc = "Field `MODE` writer - Conversion mode selection"]
197pub struct MODE_W<'a> {
198 w: &'a mut W,
199}
200impl<'a> MODE_W<'a> {
201 #[doc = r"Writes `variant` to the field"]
202 #[inline(always)]
203 pub fn variant(self, variant: MODE_A) -> &'a mut W {
204 unsafe { self.bits(variant.into()) }
205 }
206 #[doc = "8-bit conversion."]
207 #[inline(always)]
208 pub fn _00(self) -> &'a mut W {
209 self.variant(MODE_A::_00)
210 }
211 #[doc = "12-bit conversion."]
212 #[inline(always)]
213 pub fn _01(self) -> &'a mut W {
214 self.variant(MODE_A::_01)
215 }
216 #[doc = "10-bit conversion."]
217 #[inline(always)]
218 pub fn _10(self) -> &'a mut W {
219 self.variant(MODE_A::_10)
220 }
221 #[doc = r"Writes raw bits to the field"]
222 #[inline(always)]
223 pub unsafe fn bits(self, value: u8) -> &'a mut W {
224 self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
225 self.w
226 }
227}
228#[doc = "Clock Divide Select\n\nValue on reset: 0"]
229#[derive(Clone, Copy, Debug, PartialEq)]
230#[repr(u8)]
231pub enum ADIV_A {
232 #[doc = "0: The divide ratio is 1 and the clock rate is input clock."]
233 _00 = 0,
234 #[doc = "1: The divide ratio is 2 and the clock rate is (input clock)/2."]
235 _01 = 1,
236 #[doc = "2: The divide ratio is 4 and the clock rate is (input clock)/4."]
237 _10 = 2,
238 #[doc = "3: The divide ratio is 8 and the clock rate is (input clock)/8."]
239 _11 = 3,
240}
241impl From<ADIV_A> for u8 {
242 #[inline(always)]
243 fn from(variant: ADIV_A) -> Self {
244 variant as _
245 }
246}
247#[doc = "Field `ADIV` reader - Clock Divide Select"]
248pub struct ADIV_R(crate::FieldReader<u8, ADIV_A>);
249impl ADIV_R {
250 #[inline(always)]
251 pub(crate) fn new(bits: u8) -> Self {
252 ADIV_R(crate::FieldReader::new(bits))
253 }
254 #[doc = r"Get enumerated values variant"]
255 #[inline(always)]
256 pub fn variant(&self) -> ADIV_A {
257 match self.bits {
258 0 => ADIV_A::_00,
259 1 => ADIV_A::_01,
260 2 => ADIV_A::_10,
261 3 => ADIV_A::_11,
262 _ => unreachable!(),
263 }
264 }
265 #[doc = "Checks if the value of the field is `_00`"]
266 #[inline(always)]
267 pub fn is_00(&self) -> bool {
268 **self == ADIV_A::_00
269 }
270 #[doc = "Checks if the value of the field is `_01`"]
271 #[inline(always)]
272 pub fn is_01(&self) -> bool {
273 **self == ADIV_A::_01
274 }
275 #[doc = "Checks if the value of the field is `_10`"]
276 #[inline(always)]
277 pub fn is_10(&self) -> bool {
278 **self == ADIV_A::_10
279 }
280 #[doc = "Checks if the value of the field is `_11`"]
281 #[inline(always)]
282 pub fn is_11(&self) -> bool {
283 **self == ADIV_A::_11
284 }
285}
286impl core::ops::Deref for ADIV_R {
287 type Target = crate::FieldReader<u8, ADIV_A>;
288 #[inline(always)]
289 fn deref(&self) -> &Self::Target {
290 &self.0
291 }
292}
293#[doc = "Field `ADIV` writer - Clock Divide Select"]
294pub struct ADIV_W<'a> {
295 w: &'a mut W,
296}
297impl<'a> ADIV_W<'a> {
298 #[doc = r"Writes `variant` to the field"]
299 #[inline(always)]
300 pub fn variant(self, variant: ADIV_A) -> &'a mut W {
301 self.bits(variant.into())
302 }
303 #[doc = "The divide ratio is 1 and the clock rate is input clock."]
304 #[inline(always)]
305 pub fn _00(self) -> &'a mut W {
306 self.variant(ADIV_A::_00)
307 }
308 #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
309 #[inline(always)]
310 pub fn _01(self) -> &'a mut W {
311 self.variant(ADIV_A::_01)
312 }
313 #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
314 #[inline(always)]
315 pub fn _10(self) -> &'a mut W {
316 self.variant(ADIV_A::_10)
317 }
318 #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
319 #[inline(always)]
320 pub fn _11(self) -> &'a mut W {
321 self.variant(ADIV_A::_11)
322 }
323 #[doc = r"Writes raw bits to the field"]
324 #[inline(always)]
325 pub fn bits(self, value: u8) -> &'a mut W {
326 self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5);
327 self.w
328 }
329}
330#[doc = "Field `CLRLTRG` writer - Clear Latch Trigger in Trigger Handler Block"]
331pub struct CLRLTRG_W<'a> {
332 w: &'a mut W,
333}
334impl<'a> CLRLTRG_W<'a> {
335 #[doc = r"Sets the field bit"]
336 #[inline(always)]
337 pub fn set_bit(self) -> &'a mut W {
338 self.bit(true)
339 }
340 #[doc = r"Clears the field bit"]
341 #[inline(always)]
342 pub fn clear_bit(self) -> &'a mut W {
343 self.bit(false)
344 }
345 #[doc = r"Writes raw bits to the field"]
346 #[inline(always)]
347 pub fn bit(self, value: bool) -> &'a mut W {
348 self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
349 self.w
350 }
351}
352impl R {
353 #[doc = "Bits 0:1 - Input Clock Select"]
354 #[inline(always)]
355 pub fn adiclk(&self) -> ADICLK_R {
356 ADICLK_R::new((self.bits & 0x03) as u8)
357 }
358 #[doc = "Bits 2:3 - Conversion mode selection"]
359 #[inline(always)]
360 pub fn mode(&self) -> MODE_R {
361 MODE_R::new(((self.bits >> 2) & 0x03) as u8)
362 }
363 #[doc = "Bits 5:6 - Clock Divide Select"]
364 #[inline(always)]
365 pub fn adiv(&self) -> ADIV_R {
366 ADIV_R::new(((self.bits >> 5) & 0x03) as u8)
367 }
368}
369impl W {
370 #[doc = "Bits 0:1 - Input Clock Select"]
371 #[inline(always)]
372 pub fn adiclk(&mut self) -> ADICLK_W {
373 ADICLK_W { w: self }
374 }
375 #[doc = "Bits 2:3 - Conversion mode selection"]
376 #[inline(always)]
377 pub fn mode(&mut self) -> MODE_W {
378 MODE_W { w: self }
379 }
380 #[doc = "Bits 5:6 - Clock Divide Select"]
381 #[inline(always)]
382 pub fn adiv(&mut self) -> ADIV_W {
383 ADIV_W { w: self }
384 }
385 #[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
386 #[inline(always)]
387 pub fn clrltrg(&mut self) -> CLRLTRG_W {
388 CLRLTRG_W { w: self }
389 }
390 #[doc = "Writes raw bits to the register."]
391 #[inline(always)]
392 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
393 self.0.bits(bits);
394 self
395 }
396}
397#[doc = "ADC Configuration Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg1](index.html) module"]
398pub struct CFG1_SPEC;
399impl crate::RegisterSpec for CFG1_SPEC {
400 type Ux = u32;
401}
402#[doc = "`read()` method returns [cfg1::R](R) reader structure"]
403impl crate::Readable for CFG1_SPEC {
404 type Reader = R;
405}
406#[doc = "`write(|w| ..)` method takes [cfg1::W](W) writer structure"]
407impl crate::Writable for CFG1_SPEC {
408 type Writer = W;
409}
410#[doc = "`reset()` method sets CFG1 to value 0"]
411impl crate::Resettable for CFG1_SPEC {
412 #[inline(always)]
413 fn reset_value() -> Self::Ux {
414 0
415 }
416}