s32k118_pac/lpspi1/
cfgr1.rs

1#[doc = "Register `CFGR1` reader"]
2pub struct R(crate::R<CFGR1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFGR1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFGR1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFGR1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFGR1` writer"]
17pub struct W(crate::W<CFGR1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFGR1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFGR1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFGR1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Master Mode\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum MASTER_A {
40    #[doc = "0: Slave mode."]
41    _0 = 0,
42    #[doc = "1: Master mode."]
43    _1 = 1,
44}
45impl From<MASTER_A> for bool {
46    #[inline(always)]
47    fn from(variant: MASTER_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `MASTER` reader - Master Mode"]
52pub struct MASTER_R(crate::FieldReader<bool, MASTER_A>);
53impl MASTER_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        MASTER_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> MASTER_A {
61        match self.bits {
62            false => MASTER_A::_0,
63            true => MASTER_A::_1,
64        }
65    }
66    #[doc = "Checks if the value of the field is `_0`"]
67    #[inline(always)]
68    pub fn is_0(&self) -> bool {
69        **self == MASTER_A::_0
70    }
71    #[doc = "Checks if the value of the field is `_1`"]
72    #[inline(always)]
73    pub fn is_1(&self) -> bool {
74        **self == MASTER_A::_1
75    }
76}
77impl core::ops::Deref for MASTER_R {
78    type Target = crate::FieldReader<bool, MASTER_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `MASTER` writer - Master Mode"]
85pub struct MASTER_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> MASTER_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: MASTER_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Slave mode."]
95    #[inline(always)]
96    pub fn _0(self) -> &'a mut W {
97        self.variant(MASTER_A::_0)
98    }
99    #[doc = "Master mode."]
100    #[inline(always)]
101    pub fn _1(self) -> &'a mut W {
102        self.variant(MASTER_A::_1)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "Sample Point\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123pub enum SAMPLE_A {
124    #[doc = "0: Input data sampled on SCK edge."]
125    _0 = 0,
126    #[doc = "1: Input data sampled on delayed SCK edge."]
127    _1 = 1,
128}
129impl From<SAMPLE_A> for bool {
130    #[inline(always)]
131    fn from(variant: SAMPLE_A) -> Self {
132        variant as u8 != 0
133    }
134}
135#[doc = "Field `SAMPLE` reader - Sample Point"]
136pub struct SAMPLE_R(crate::FieldReader<bool, SAMPLE_A>);
137impl SAMPLE_R {
138    #[inline(always)]
139    pub(crate) fn new(bits: bool) -> Self {
140        SAMPLE_R(crate::FieldReader::new(bits))
141    }
142    #[doc = r"Get enumerated values variant"]
143    #[inline(always)]
144    pub fn variant(&self) -> SAMPLE_A {
145        match self.bits {
146            false => SAMPLE_A::_0,
147            true => SAMPLE_A::_1,
148        }
149    }
150    #[doc = "Checks if the value of the field is `_0`"]
151    #[inline(always)]
152    pub fn is_0(&self) -> bool {
153        **self == SAMPLE_A::_0
154    }
155    #[doc = "Checks if the value of the field is `_1`"]
156    #[inline(always)]
157    pub fn is_1(&self) -> bool {
158        **self == SAMPLE_A::_1
159    }
160}
161impl core::ops::Deref for SAMPLE_R {
162    type Target = crate::FieldReader<bool, SAMPLE_A>;
163    #[inline(always)]
164    fn deref(&self) -> &Self::Target {
165        &self.0
166    }
167}
168#[doc = "Field `SAMPLE` writer - Sample Point"]
169pub struct SAMPLE_W<'a> {
170    w: &'a mut W,
171}
172impl<'a> SAMPLE_W<'a> {
173    #[doc = r"Writes `variant` to the field"]
174    #[inline(always)]
175    pub fn variant(self, variant: SAMPLE_A) -> &'a mut W {
176        self.bit(variant.into())
177    }
178    #[doc = "Input data sampled on SCK edge."]
179    #[inline(always)]
180    pub fn _0(self) -> &'a mut W {
181        self.variant(SAMPLE_A::_0)
182    }
183    #[doc = "Input data sampled on delayed SCK edge."]
184    #[inline(always)]
185    pub fn _1(self) -> &'a mut W {
186        self.variant(SAMPLE_A::_1)
187    }
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
202        self.w
203    }
204}
205#[doc = "Automatic PCS\n\nValue on reset: 0"]
206#[derive(Clone, Copy, Debug, PartialEq)]
207pub enum AUTOPCS_A {
208    #[doc = "0: Automatic PCS generation disabled."]
209    _0 = 0,
210    #[doc = "1: Automatic PCS generation enabled."]
211    _1 = 1,
212}
213impl From<AUTOPCS_A> for bool {
214    #[inline(always)]
215    fn from(variant: AUTOPCS_A) -> Self {
216        variant as u8 != 0
217    }
218}
219#[doc = "Field `AUTOPCS` reader - Automatic PCS"]
220pub struct AUTOPCS_R(crate::FieldReader<bool, AUTOPCS_A>);
221impl AUTOPCS_R {
222    #[inline(always)]
223    pub(crate) fn new(bits: bool) -> Self {
224        AUTOPCS_R(crate::FieldReader::new(bits))
225    }
226    #[doc = r"Get enumerated values variant"]
227    #[inline(always)]
228    pub fn variant(&self) -> AUTOPCS_A {
229        match self.bits {
230            false => AUTOPCS_A::_0,
231            true => AUTOPCS_A::_1,
232        }
233    }
234    #[doc = "Checks if the value of the field is `_0`"]
235    #[inline(always)]
236    pub fn is_0(&self) -> bool {
237        **self == AUTOPCS_A::_0
238    }
239    #[doc = "Checks if the value of the field is `_1`"]
240    #[inline(always)]
241    pub fn is_1(&self) -> bool {
242        **self == AUTOPCS_A::_1
243    }
244}
245impl core::ops::Deref for AUTOPCS_R {
246    type Target = crate::FieldReader<bool, AUTOPCS_A>;
247    #[inline(always)]
248    fn deref(&self) -> &Self::Target {
249        &self.0
250    }
251}
252#[doc = "Field `AUTOPCS` writer - Automatic PCS"]
253pub struct AUTOPCS_W<'a> {
254    w: &'a mut W,
255}
256impl<'a> AUTOPCS_W<'a> {
257    #[doc = r"Writes `variant` to the field"]
258    #[inline(always)]
259    pub fn variant(self, variant: AUTOPCS_A) -> &'a mut W {
260        self.bit(variant.into())
261    }
262    #[doc = "Automatic PCS generation disabled."]
263    #[inline(always)]
264    pub fn _0(self) -> &'a mut W {
265        self.variant(AUTOPCS_A::_0)
266    }
267    #[doc = "Automatic PCS generation enabled."]
268    #[inline(always)]
269    pub fn _1(self) -> &'a mut W {
270        self.variant(AUTOPCS_A::_1)
271    }
272    #[doc = r"Sets the field bit"]
273    #[inline(always)]
274    pub fn set_bit(self) -> &'a mut W {
275        self.bit(true)
276    }
277    #[doc = r"Clears the field bit"]
278    #[inline(always)]
279    pub fn clear_bit(self) -> &'a mut W {
280        self.bit(false)
281    }
282    #[doc = r"Writes raw bits to the field"]
283    #[inline(always)]
284    pub fn bit(self, value: bool) -> &'a mut W {
285        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
286        self.w
287    }
288}
289#[doc = "No Stall\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq)]
291pub enum NOSTALL_A {
292    #[doc = "0: Transfers will stall when transmit FIFO is empty or receive FIFO is full."]
293    _0 = 0,
294    #[doc = "1: Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."]
295    _1 = 1,
296}
297impl From<NOSTALL_A> for bool {
298    #[inline(always)]
299    fn from(variant: NOSTALL_A) -> Self {
300        variant as u8 != 0
301    }
302}
303#[doc = "Field `NOSTALL` reader - No Stall"]
304pub struct NOSTALL_R(crate::FieldReader<bool, NOSTALL_A>);
305impl NOSTALL_R {
306    #[inline(always)]
307    pub(crate) fn new(bits: bool) -> Self {
308        NOSTALL_R(crate::FieldReader::new(bits))
309    }
310    #[doc = r"Get enumerated values variant"]
311    #[inline(always)]
312    pub fn variant(&self) -> NOSTALL_A {
313        match self.bits {
314            false => NOSTALL_A::_0,
315            true => NOSTALL_A::_1,
316        }
317    }
318    #[doc = "Checks if the value of the field is `_0`"]
319    #[inline(always)]
320    pub fn is_0(&self) -> bool {
321        **self == NOSTALL_A::_0
322    }
323    #[doc = "Checks if the value of the field is `_1`"]
324    #[inline(always)]
325    pub fn is_1(&self) -> bool {
326        **self == NOSTALL_A::_1
327    }
328}
329impl core::ops::Deref for NOSTALL_R {
330    type Target = crate::FieldReader<bool, NOSTALL_A>;
331    #[inline(always)]
332    fn deref(&self) -> &Self::Target {
333        &self.0
334    }
335}
336#[doc = "Field `NOSTALL` writer - No Stall"]
337pub struct NOSTALL_W<'a> {
338    w: &'a mut W,
339}
340impl<'a> NOSTALL_W<'a> {
341    #[doc = r"Writes `variant` to the field"]
342    #[inline(always)]
343    pub fn variant(self, variant: NOSTALL_A) -> &'a mut W {
344        self.bit(variant.into())
345    }
346    #[doc = "Transfers will stall when transmit FIFO is empty or receive FIFO is full."]
347    #[inline(always)]
348    pub fn _0(self) -> &'a mut W {
349        self.variant(NOSTALL_A::_0)
350    }
351    #[doc = "Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur."]
352    #[inline(always)]
353    pub fn _1(self) -> &'a mut W {
354        self.variant(NOSTALL_A::_1)
355    }
356    #[doc = r"Sets the field bit"]
357    #[inline(always)]
358    pub fn set_bit(self) -> &'a mut W {
359        self.bit(true)
360    }
361    #[doc = r"Clears the field bit"]
362    #[inline(always)]
363    pub fn clear_bit(self) -> &'a mut W {
364        self.bit(false)
365    }
366    #[doc = r"Writes raw bits to the field"]
367    #[inline(always)]
368    pub fn bit(self, value: bool) -> &'a mut W {
369        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
370        self.w
371    }
372}
373#[doc = "Peripheral Chip Select Polarity\n\nValue on reset: 0"]
374#[derive(Clone, Copy, Debug, PartialEq)]
375#[repr(u8)]
376pub enum PCSPOL_A {
377    #[doc = "0: The PCSx is active low."]
378    _0000 = 0,
379    #[doc = "1: The PCSx is active high."]
380    _0001 = 1,
381}
382impl From<PCSPOL_A> for u8 {
383    #[inline(always)]
384    fn from(variant: PCSPOL_A) -> Self {
385        variant as _
386    }
387}
388#[doc = "Field `PCSPOL` reader - Peripheral Chip Select Polarity"]
389pub struct PCSPOL_R(crate::FieldReader<u8, PCSPOL_A>);
390impl PCSPOL_R {
391    #[inline(always)]
392    pub(crate) fn new(bits: u8) -> Self {
393        PCSPOL_R(crate::FieldReader::new(bits))
394    }
395    #[doc = r"Get enumerated values variant"]
396    #[inline(always)]
397    pub fn variant(&self) -> Option<PCSPOL_A> {
398        match self.bits {
399            0 => Some(PCSPOL_A::_0000),
400            1 => Some(PCSPOL_A::_0001),
401            _ => None,
402        }
403    }
404    #[doc = "Checks if the value of the field is `_0000`"]
405    #[inline(always)]
406    pub fn is_0000(&self) -> bool {
407        **self == PCSPOL_A::_0000
408    }
409    #[doc = "Checks if the value of the field is `_0001`"]
410    #[inline(always)]
411    pub fn is_0001(&self) -> bool {
412        **self == PCSPOL_A::_0001
413    }
414}
415impl core::ops::Deref for PCSPOL_R {
416    type Target = crate::FieldReader<u8, PCSPOL_A>;
417    #[inline(always)]
418    fn deref(&self) -> &Self::Target {
419        &self.0
420    }
421}
422#[doc = "Field `PCSPOL` writer - Peripheral Chip Select Polarity"]
423pub struct PCSPOL_W<'a> {
424    w: &'a mut W,
425}
426impl<'a> PCSPOL_W<'a> {
427    #[doc = r"Writes `variant` to the field"]
428    #[inline(always)]
429    pub fn variant(self, variant: PCSPOL_A) -> &'a mut W {
430        unsafe { self.bits(variant.into()) }
431    }
432    #[doc = "The PCSx is active low."]
433    #[inline(always)]
434    pub fn _0000(self) -> &'a mut W {
435        self.variant(PCSPOL_A::_0000)
436    }
437    #[doc = "The PCSx is active high."]
438    #[inline(always)]
439    pub fn _0001(self) -> &'a mut W {
440        self.variant(PCSPOL_A::_0001)
441    }
442    #[doc = r"Writes raw bits to the field"]
443    #[inline(always)]
444    pub unsafe fn bits(self, value: u8) -> &'a mut W {
445        self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8);
446        self.w
447    }
448}
449#[doc = "Match Configuration\n\nValue on reset: 0"]
450#[derive(Clone, Copy, Debug, PartialEq)]
451#[repr(u8)]
452pub enum MATCFG_A {
453    #[doc = "0: Match is disabled."]
454    _000 = 0,
455    #[doc = "2: 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"]
456    _010 = 2,
457    #[doc = "3: 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"]
458    _011 = 3,
459    #[doc = "4: 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., \\[(1st data word = MATCH0) * (2nd data word = MATCH1)\\]"]
460    _100 = 4,
461    #[doc = "5: 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., \\[(any data word = MATCH0) * (next data word = MATCH1)\\]"]
462    _101 = 5,
463    #[doc = "6: 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(1st data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
464    _110 = 6,
465    #[doc = "7: 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(any data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
466    _111 = 7,
467}
468impl From<MATCFG_A> for u8 {
469    #[inline(always)]
470    fn from(variant: MATCFG_A) -> Self {
471        variant as _
472    }
473}
474#[doc = "Field `MATCFG` reader - Match Configuration"]
475pub struct MATCFG_R(crate::FieldReader<u8, MATCFG_A>);
476impl MATCFG_R {
477    #[inline(always)]
478    pub(crate) fn new(bits: u8) -> Self {
479        MATCFG_R(crate::FieldReader::new(bits))
480    }
481    #[doc = r"Get enumerated values variant"]
482    #[inline(always)]
483    pub fn variant(&self) -> Option<MATCFG_A> {
484        match self.bits {
485            0 => Some(MATCFG_A::_000),
486            2 => Some(MATCFG_A::_010),
487            3 => Some(MATCFG_A::_011),
488            4 => Some(MATCFG_A::_100),
489            5 => Some(MATCFG_A::_101),
490            6 => Some(MATCFG_A::_110),
491            7 => Some(MATCFG_A::_111),
492            _ => None,
493        }
494    }
495    #[doc = "Checks if the value of the field is `_000`"]
496    #[inline(always)]
497    pub fn is_000(&self) -> bool {
498        **self == MATCFG_A::_000
499    }
500    #[doc = "Checks if the value of the field is `_010`"]
501    #[inline(always)]
502    pub fn is_010(&self) -> bool {
503        **self == MATCFG_A::_010
504    }
505    #[doc = "Checks if the value of the field is `_011`"]
506    #[inline(always)]
507    pub fn is_011(&self) -> bool {
508        **self == MATCFG_A::_011
509    }
510    #[doc = "Checks if the value of the field is `_100`"]
511    #[inline(always)]
512    pub fn is_100(&self) -> bool {
513        **self == MATCFG_A::_100
514    }
515    #[doc = "Checks if the value of the field is `_101`"]
516    #[inline(always)]
517    pub fn is_101(&self) -> bool {
518        **self == MATCFG_A::_101
519    }
520    #[doc = "Checks if the value of the field is `_110`"]
521    #[inline(always)]
522    pub fn is_110(&self) -> bool {
523        **self == MATCFG_A::_110
524    }
525    #[doc = "Checks if the value of the field is `_111`"]
526    #[inline(always)]
527    pub fn is_111(&self) -> bool {
528        **self == MATCFG_A::_111
529    }
530}
531impl core::ops::Deref for MATCFG_R {
532    type Target = crate::FieldReader<u8, MATCFG_A>;
533    #[inline(always)]
534    fn deref(&self) -> &Self::Target {
535        &self.0
536    }
537}
538#[doc = "Field `MATCFG` writer - Match Configuration"]
539pub struct MATCFG_W<'a> {
540    w: &'a mut W,
541}
542impl<'a> MATCFG_W<'a> {
543    #[doc = r"Writes `variant` to the field"]
544    #[inline(always)]
545    pub fn variant(self, variant: MATCFG_A) -> &'a mut W {
546        unsafe { self.bits(variant.into()) }
547    }
548    #[doc = "Match is disabled."]
549    #[inline(always)]
550    pub fn _000(self) -> &'a mut W {
551        self.variant(MATCFG_A::_000)
552    }
553    #[doc = "010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)"]
554    #[inline(always)]
555    pub fn _010(self) -> &'a mut W {
556        self.variant(MATCFG_A::_010)
557    }
558    #[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"]
559    #[inline(always)]
560    pub fn _011(self) -> &'a mut W {
561        self.variant(MATCFG_A::_011)
562    }
563    #[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., \\[(1st data word = MATCH0) * (2nd data word = MATCH1)\\]"]
564    #[inline(always)]
565    pub fn _100(self) -> &'a mut W {
566        self.variant(MATCFG_A::_100)
567    }
568    #[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., \\[(any data word = MATCH0) * (next data word = MATCH1)\\]"]
569    #[inline(always)]
570    pub fn _101(self) -> &'a mut W {
571        self.variant(MATCFG_A::_101)
572    }
573    #[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(1st data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
574    #[inline(always)]
575    pub fn _110(self) -> &'a mut W {
576        self.variant(MATCFG_A::_110)
577    }
578    #[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(any data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
579    #[inline(always)]
580    pub fn _111(self) -> &'a mut W {
581        self.variant(MATCFG_A::_111)
582    }
583    #[doc = r"Writes raw bits to the field"]
584    #[inline(always)]
585    pub unsafe fn bits(self, value: u8) -> &'a mut W {
586        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
587        self.w
588    }
589}
590#[doc = "Pin Configuration\n\nValue on reset: 0"]
591#[derive(Clone, Copy, Debug, PartialEq)]
592#[repr(u8)]
593pub enum PINCFG_A {
594    #[doc = "0: SIN is used for input data and SOUT for output data."]
595    _00 = 0,
596    #[doc = "1: SIN is used for both input and output data."]
597    _01 = 1,
598    #[doc = "2: SOUT is used for both input and output data."]
599    _10 = 2,
600    #[doc = "3: SOUT is used for input data and SIN for output data."]
601    _11 = 3,
602}
603impl From<PINCFG_A> for u8 {
604    #[inline(always)]
605    fn from(variant: PINCFG_A) -> Self {
606        variant as _
607    }
608}
609#[doc = "Field `PINCFG` reader - Pin Configuration"]
610pub struct PINCFG_R(crate::FieldReader<u8, PINCFG_A>);
611impl PINCFG_R {
612    #[inline(always)]
613    pub(crate) fn new(bits: u8) -> Self {
614        PINCFG_R(crate::FieldReader::new(bits))
615    }
616    #[doc = r"Get enumerated values variant"]
617    #[inline(always)]
618    pub fn variant(&self) -> PINCFG_A {
619        match self.bits {
620            0 => PINCFG_A::_00,
621            1 => PINCFG_A::_01,
622            2 => PINCFG_A::_10,
623            3 => PINCFG_A::_11,
624            _ => unreachable!(),
625        }
626    }
627    #[doc = "Checks if the value of the field is `_00`"]
628    #[inline(always)]
629    pub fn is_00(&self) -> bool {
630        **self == PINCFG_A::_00
631    }
632    #[doc = "Checks if the value of the field is `_01`"]
633    #[inline(always)]
634    pub fn is_01(&self) -> bool {
635        **self == PINCFG_A::_01
636    }
637    #[doc = "Checks if the value of the field is `_10`"]
638    #[inline(always)]
639    pub fn is_10(&self) -> bool {
640        **self == PINCFG_A::_10
641    }
642    #[doc = "Checks if the value of the field is `_11`"]
643    #[inline(always)]
644    pub fn is_11(&self) -> bool {
645        **self == PINCFG_A::_11
646    }
647}
648impl core::ops::Deref for PINCFG_R {
649    type Target = crate::FieldReader<u8, PINCFG_A>;
650    #[inline(always)]
651    fn deref(&self) -> &Self::Target {
652        &self.0
653    }
654}
655#[doc = "Field `PINCFG` writer - Pin Configuration"]
656pub struct PINCFG_W<'a> {
657    w: &'a mut W,
658}
659impl<'a> PINCFG_W<'a> {
660    #[doc = r"Writes `variant` to the field"]
661    #[inline(always)]
662    pub fn variant(self, variant: PINCFG_A) -> &'a mut W {
663        self.bits(variant.into())
664    }
665    #[doc = "SIN is used for input data and SOUT for output data."]
666    #[inline(always)]
667    pub fn _00(self) -> &'a mut W {
668        self.variant(PINCFG_A::_00)
669    }
670    #[doc = "SIN is used for both input and output data."]
671    #[inline(always)]
672    pub fn _01(self) -> &'a mut W {
673        self.variant(PINCFG_A::_01)
674    }
675    #[doc = "SOUT is used for both input and output data."]
676    #[inline(always)]
677    pub fn _10(self) -> &'a mut W {
678        self.variant(PINCFG_A::_10)
679    }
680    #[doc = "SOUT is used for input data and SIN for output data."]
681    #[inline(always)]
682    pub fn _11(self) -> &'a mut W {
683        self.variant(PINCFG_A::_11)
684    }
685    #[doc = r"Writes raw bits to the field"]
686    #[inline(always)]
687    pub fn bits(self, value: u8) -> &'a mut W {
688        self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24);
689        self.w
690    }
691}
692#[doc = "Output Config\n\nValue on reset: 0"]
693#[derive(Clone, Copy, Debug, PartialEq)]
694pub enum OUTCFG_A {
695    #[doc = "0: Output data retains last value when chip select is negated."]
696    _0 = 0,
697    #[doc = "1: Output data is tristated when chip select is negated."]
698    _1 = 1,
699}
700impl From<OUTCFG_A> for bool {
701    #[inline(always)]
702    fn from(variant: OUTCFG_A) -> Self {
703        variant as u8 != 0
704    }
705}
706#[doc = "Field `OUTCFG` reader - Output Config"]
707pub struct OUTCFG_R(crate::FieldReader<bool, OUTCFG_A>);
708impl OUTCFG_R {
709    #[inline(always)]
710    pub(crate) fn new(bits: bool) -> Self {
711        OUTCFG_R(crate::FieldReader::new(bits))
712    }
713    #[doc = r"Get enumerated values variant"]
714    #[inline(always)]
715    pub fn variant(&self) -> OUTCFG_A {
716        match self.bits {
717            false => OUTCFG_A::_0,
718            true => OUTCFG_A::_1,
719        }
720    }
721    #[doc = "Checks if the value of the field is `_0`"]
722    #[inline(always)]
723    pub fn is_0(&self) -> bool {
724        **self == OUTCFG_A::_0
725    }
726    #[doc = "Checks if the value of the field is `_1`"]
727    #[inline(always)]
728    pub fn is_1(&self) -> bool {
729        **self == OUTCFG_A::_1
730    }
731}
732impl core::ops::Deref for OUTCFG_R {
733    type Target = crate::FieldReader<bool, OUTCFG_A>;
734    #[inline(always)]
735    fn deref(&self) -> &Self::Target {
736        &self.0
737    }
738}
739#[doc = "Field `OUTCFG` writer - Output Config"]
740pub struct OUTCFG_W<'a> {
741    w: &'a mut W,
742}
743impl<'a> OUTCFG_W<'a> {
744    #[doc = r"Writes `variant` to the field"]
745    #[inline(always)]
746    pub fn variant(self, variant: OUTCFG_A) -> &'a mut W {
747        self.bit(variant.into())
748    }
749    #[doc = "Output data retains last value when chip select is negated."]
750    #[inline(always)]
751    pub fn _0(self) -> &'a mut W {
752        self.variant(OUTCFG_A::_0)
753    }
754    #[doc = "Output data is tristated when chip select is negated."]
755    #[inline(always)]
756    pub fn _1(self) -> &'a mut W {
757        self.variant(OUTCFG_A::_1)
758    }
759    #[doc = r"Sets the field bit"]
760    #[inline(always)]
761    pub fn set_bit(self) -> &'a mut W {
762        self.bit(true)
763    }
764    #[doc = r"Clears the field bit"]
765    #[inline(always)]
766    pub fn clear_bit(self) -> &'a mut W {
767        self.bit(false)
768    }
769    #[doc = r"Writes raw bits to the field"]
770    #[inline(always)]
771    pub fn bit(self, value: bool) -> &'a mut W {
772        self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26);
773        self.w
774    }
775}
776#[doc = "Peripheral Chip Select Configuration\n\nValue on reset: 0"]
777#[derive(Clone, Copy, Debug, PartialEq)]
778pub enum PCSCFG_A {
779    #[doc = "0: PCS\\[3:2\\]
780are enabled."]
781    _0 = 0,
782    #[doc = "1: PCS\\[3:2\\]
783are disabled."]
784    _1 = 1,
785}
786impl From<PCSCFG_A> for bool {
787    #[inline(always)]
788    fn from(variant: PCSCFG_A) -> Self {
789        variant as u8 != 0
790    }
791}
792#[doc = "Field `PCSCFG` reader - Peripheral Chip Select Configuration"]
793pub struct PCSCFG_R(crate::FieldReader<bool, PCSCFG_A>);
794impl PCSCFG_R {
795    #[inline(always)]
796    pub(crate) fn new(bits: bool) -> Self {
797        PCSCFG_R(crate::FieldReader::new(bits))
798    }
799    #[doc = r"Get enumerated values variant"]
800    #[inline(always)]
801    pub fn variant(&self) -> PCSCFG_A {
802        match self.bits {
803            false => PCSCFG_A::_0,
804            true => PCSCFG_A::_1,
805        }
806    }
807    #[doc = "Checks if the value of the field is `_0`"]
808    #[inline(always)]
809    pub fn is_0(&self) -> bool {
810        **self == PCSCFG_A::_0
811    }
812    #[doc = "Checks if the value of the field is `_1`"]
813    #[inline(always)]
814    pub fn is_1(&self) -> bool {
815        **self == PCSCFG_A::_1
816    }
817}
818impl core::ops::Deref for PCSCFG_R {
819    type Target = crate::FieldReader<bool, PCSCFG_A>;
820    #[inline(always)]
821    fn deref(&self) -> &Self::Target {
822        &self.0
823    }
824}
825#[doc = "Field `PCSCFG` writer - Peripheral Chip Select Configuration"]
826pub struct PCSCFG_W<'a> {
827    w: &'a mut W,
828}
829impl<'a> PCSCFG_W<'a> {
830    #[doc = r"Writes `variant` to the field"]
831    #[inline(always)]
832    pub fn variant(self, variant: PCSCFG_A) -> &'a mut W {
833        self.bit(variant.into())
834    }
835    #[doc = "PCS\\[3:2\\]
836are enabled."]
837    #[inline(always)]
838    pub fn _0(self) -> &'a mut W {
839        self.variant(PCSCFG_A::_0)
840    }
841    #[doc = "PCS\\[3:2\\]
842are disabled."]
843    #[inline(always)]
844    pub fn _1(self) -> &'a mut W {
845        self.variant(PCSCFG_A::_1)
846    }
847    #[doc = r"Sets the field bit"]
848    #[inline(always)]
849    pub fn set_bit(self) -> &'a mut W {
850        self.bit(true)
851    }
852    #[doc = r"Clears the field bit"]
853    #[inline(always)]
854    pub fn clear_bit(self) -> &'a mut W {
855        self.bit(false)
856    }
857    #[doc = r"Writes raw bits to the field"]
858    #[inline(always)]
859    pub fn bit(self, value: bool) -> &'a mut W {
860        self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27);
861        self.w
862    }
863}
864impl R {
865    #[doc = "Bit 0 - Master Mode"]
866    #[inline(always)]
867    pub fn master(&self) -> MASTER_R {
868        MASTER_R::new((self.bits & 0x01) != 0)
869    }
870    #[doc = "Bit 1 - Sample Point"]
871    #[inline(always)]
872    pub fn sample(&self) -> SAMPLE_R {
873        SAMPLE_R::new(((self.bits >> 1) & 0x01) != 0)
874    }
875    #[doc = "Bit 2 - Automatic PCS"]
876    #[inline(always)]
877    pub fn autopcs(&self) -> AUTOPCS_R {
878        AUTOPCS_R::new(((self.bits >> 2) & 0x01) != 0)
879    }
880    #[doc = "Bit 3 - No Stall"]
881    #[inline(always)]
882    pub fn nostall(&self) -> NOSTALL_R {
883        NOSTALL_R::new(((self.bits >> 3) & 0x01) != 0)
884    }
885    #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"]
886    #[inline(always)]
887    pub fn pcspol(&self) -> PCSPOL_R {
888        PCSPOL_R::new(((self.bits >> 8) & 0x0f) as u8)
889    }
890    #[doc = "Bits 16:18 - Match Configuration"]
891    #[inline(always)]
892    pub fn matcfg(&self) -> MATCFG_R {
893        MATCFG_R::new(((self.bits >> 16) & 0x07) as u8)
894    }
895    #[doc = "Bits 24:25 - Pin Configuration"]
896    #[inline(always)]
897    pub fn pincfg(&self) -> PINCFG_R {
898        PINCFG_R::new(((self.bits >> 24) & 0x03) as u8)
899    }
900    #[doc = "Bit 26 - Output Config"]
901    #[inline(always)]
902    pub fn outcfg(&self) -> OUTCFG_R {
903        OUTCFG_R::new(((self.bits >> 26) & 0x01) != 0)
904    }
905    #[doc = "Bit 27 - Peripheral Chip Select Configuration"]
906    #[inline(always)]
907    pub fn pcscfg(&self) -> PCSCFG_R {
908        PCSCFG_R::new(((self.bits >> 27) & 0x01) != 0)
909    }
910}
911impl W {
912    #[doc = "Bit 0 - Master Mode"]
913    #[inline(always)]
914    pub fn master(&mut self) -> MASTER_W {
915        MASTER_W { w: self }
916    }
917    #[doc = "Bit 1 - Sample Point"]
918    #[inline(always)]
919    pub fn sample(&mut self) -> SAMPLE_W {
920        SAMPLE_W { w: self }
921    }
922    #[doc = "Bit 2 - Automatic PCS"]
923    #[inline(always)]
924    pub fn autopcs(&mut self) -> AUTOPCS_W {
925        AUTOPCS_W { w: self }
926    }
927    #[doc = "Bit 3 - No Stall"]
928    #[inline(always)]
929    pub fn nostall(&mut self) -> NOSTALL_W {
930        NOSTALL_W { w: self }
931    }
932    #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"]
933    #[inline(always)]
934    pub fn pcspol(&mut self) -> PCSPOL_W {
935        PCSPOL_W { w: self }
936    }
937    #[doc = "Bits 16:18 - Match Configuration"]
938    #[inline(always)]
939    pub fn matcfg(&mut self) -> MATCFG_W {
940        MATCFG_W { w: self }
941    }
942    #[doc = "Bits 24:25 - Pin Configuration"]
943    #[inline(always)]
944    pub fn pincfg(&mut self) -> PINCFG_W {
945        PINCFG_W { w: self }
946    }
947    #[doc = "Bit 26 - Output Config"]
948    #[inline(always)]
949    pub fn outcfg(&mut self) -> OUTCFG_W {
950        OUTCFG_W { w: self }
951    }
952    #[doc = "Bit 27 - Peripheral Chip Select Configuration"]
953    #[inline(always)]
954    pub fn pcscfg(&mut self) -> PCSCFG_W {
955        PCSCFG_W { w: self }
956    }
957    #[doc = "Writes raw bits to the register."]
958    #[inline(always)]
959    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
960        self.0.bits(bits);
961        self
962    }
963}
964#[doc = "Configuration Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr1](index.html) module"]
965pub struct CFGR1_SPEC;
966impl crate::RegisterSpec for CFGR1_SPEC {
967    type Ux = u32;
968}
969#[doc = "`read()` method returns [cfgr1::R](R) reader structure"]
970impl crate::Readable for CFGR1_SPEC {
971    type Reader = R;
972}
973#[doc = "`write(|w| ..)` method takes [cfgr1::W](W) writer structure"]
974impl crate::Writable for CFGR1_SPEC {
975    type Writer = W;
976}
977#[doc = "`reset()` method sets CFGR1 to value 0"]
978impl crate::Resettable for CFGR1_SPEC {
979    #[inline(always)]
980    fn reset_value() -> Self::Ux {
981        0
982    }
983}
s32k118_pac/lpspi1/cfgr1.rs

s32k118_pac/lpspi1/
cfgr1.rs
