s32k116_pac/can0/
fdctrl.rs

1#[doc = "Register `FDCTRL` reader"]
2pub struct R(crate::R<FDCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FDCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FDCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FDCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FDCTRL` writer"]
17pub struct W(crate::W<FDCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FDCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FDCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FDCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TDCVAL` reader - Transceiver Delay Compensation Value"]
38pub struct TDCVAL_R(crate::FieldReader<u8, u8>);
39impl TDCVAL_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u8) -> Self {
42        TDCVAL_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for TDCVAL_R {
46    type Target = crate::FieldReader<u8, u8>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `TDCOFF` reader - Transceiver Delay Compensation Offset"]
53pub struct TDCOFF_R(crate::FieldReader<u8, u8>);
54impl TDCOFF_R {
55    #[inline(always)]
56    pub(crate) fn new(bits: u8) -> Self {
57        TDCOFF_R(crate::FieldReader::new(bits))
58    }
59}
60impl core::ops::Deref for TDCOFF_R {
61    type Target = crate::FieldReader<u8, u8>;
62    #[inline(always)]
63    fn deref(&self) -> &Self::Target {
64        &self.0
65    }
66}
67#[doc = "Field `TDCOFF` writer - Transceiver Delay Compensation Offset"]
68pub struct TDCOFF_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> TDCOFF_W<'a> {
72    #[doc = r"Writes raw bits to the field"]
73    #[inline(always)]
74    pub unsafe fn bits(self, value: u8) -> &'a mut W {
75        self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8);
76        self.w
77    }
78}
79#[doc = "Transceiver Delay Compensation Fail\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq)]
81pub enum TDCFAIL_A {
82    #[doc = "0: Measured loop delay is in range."]
83    _0 = 0,
84    #[doc = "1: Measured loop delay is out of range."]
85    _1 = 1,
86}
87impl From<TDCFAIL_A> for bool {
88    #[inline(always)]
89    fn from(variant: TDCFAIL_A) -> Self {
90        variant as u8 != 0
91    }
92}
93#[doc = "Field `TDCFAIL` reader - Transceiver Delay Compensation Fail"]
94pub struct TDCFAIL_R(crate::FieldReader<bool, TDCFAIL_A>);
95impl TDCFAIL_R {
96    #[inline(always)]
97    pub(crate) fn new(bits: bool) -> Self {
98        TDCFAIL_R(crate::FieldReader::new(bits))
99    }
100    #[doc = r"Get enumerated values variant"]
101    #[inline(always)]
102    pub fn variant(&self) -> TDCFAIL_A {
103        match self.bits {
104            false => TDCFAIL_A::_0,
105            true => TDCFAIL_A::_1,
106        }
107    }
108    #[doc = "Checks if the value of the field is `_0`"]
109    #[inline(always)]
110    pub fn is_0(&self) -> bool {
111        **self == TDCFAIL_A::_0
112    }
113    #[doc = "Checks if the value of the field is `_1`"]
114    #[inline(always)]
115    pub fn is_1(&self) -> bool {
116        **self == TDCFAIL_A::_1
117    }
118}
119impl core::ops::Deref for TDCFAIL_R {
120    type Target = crate::FieldReader<bool, TDCFAIL_A>;
121    #[inline(always)]
122    fn deref(&self) -> &Self::Target {
123        &self.0
124    }
125}
126#[doc = "Field `TDCFAIL` writer - Transceiver Delay Compensation Fail"]
127pub struct TDCFAIL_W<'a> {
128    w: &'a mut W,
129}
130impl<'a> TDCFAIL_W<'a> {
131    #[doc = r"Writes `variant` to the field"]
132    #[inline(always)]
133    pub fn variant(self, variant: TDCFAIL_A) -> &'a mut W {
134        self.bit(variant.into())
135    }
136    #[doc = "Measured loop delay is in range."]
137    #[inline(always)]
138    pub fn _0(self) -> &'a mut W {
139        self.variant(TDCFAIL_A::_0)
140    }
141    #[doc = "Measured loop delay is out of range."]
142    #[inline(always)]
143    pub fn _1(self) -> &'a mut W {
144        self.variant(TDCFAIL_A::_1)
145    }
146    #[doc = r"Sets the field bit"]
147    #[inline(always)]
148    pub fn set_bit(self) -> &'a mut W {
149        self.bit(true)
150    }
151    #[doc = r"Clears the field bit"]
152    #[inline(always)]
153    pub fn clear_bit(self) -> &'a mut W {
154        self.bit(false)
155    }
156    #[doc = r"Writes raw bits to the field"]
157    #[inline(always)]
158    pub fn bit(self, value: bool) -> &'a mut W {
159        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
160        self.w
161    }
162}
163#[doc = "Transceiver Delay Compensation Enable\n\nValue on reset: 0"]
164#[derive(Clone, Copy, Debug, PartialEq)]
165pub enum TDCEN_A {
166    #[doc = "0: TDC is disabled"]
167    _0 = 0,
168    #[doc = "1: TDC is enabled"]
169    _1 = 1,
170}
171impl From<TDCEN_A> for bool {
172    #[inline(always)]
173    fn from(variant: TDCEN_A) -> Self {
174        variant as u8 != 0
175    }
176}
177#[doc = "Field `TDCEN` reader - Transceiver Delay Compensation Enable"]
178pub struct TDCEN_R(crate::FieldReader<bool, TDCEN_A>);
179impl TDCEN_R {
180    #[inline(always)]
181    pub(crate) fn new(bits: bool) -> Self {
182        TDCEN_R(crate::FieldReader::new(bits))
183    }
184    #[doc = r"Get enumerated values variant"]
185    #[inline(always)]
186    pub fn variant(&self) -> TDCEN_A {
187        match self.bits {
188            false => TDCEN_A::_0,
189            true => TDCEN_A::_1,
190        }
191    }
192    #[doc = "Checks if the value of the field is `_0`"]
193    #[inline(always)]
194    pub fn is_0(&self) -> bool {
195        **self == TDCEN_A::_0
196    }
197    #[doc = "Checks if the value of the field is `_1`"]
198    #[inline(always)]
199    pub fn is_1(&self) -> bool {
200        **self == TDCEN_A::_1
201    }
202}
203impl core::ops::Deref for TDCEN_R {
204    type Target = crate::FieldReader<bool, TDCEN_A>;
205    #[inline(always)]
206    fn deref(&self) -> &Self::Target {
207        &self.0
208    }
209}
210#[doc = "Field `TDCEN` writer - Transceiver Delay Compensation Enable"]
211pub struct TDCEN_W<'a> {
212    w: &'a mut W,
213}
214impl<'a> TDCEN_W<'a> {
215    #[doc = r"Writes `variant` to the field"]
216    #[inline(always)]
217    pub fn variant(self, variant: TDCEN_A) -> &'a mut W {
218        self.bit(variant.into())
219    }
220    #[doc = "TDC is disabled"]
221    #[inline(always)]
222    pub fn _0(self) -> &'a mut W {
223        self.variant(TDCEN_A::_0)
224    }
225    #[doc = "TDC is enabled"]
226    #[inline(always)]
227    pub fn _1(self) -> &'a mut W {
228        self.variant(TDCEN_A::_1)
229    }
230    #[doc = r"Sets the field bit"]
231    #[inline(always)]
232    pub fn set_bit(self) -> &'a mut W {
233        self.bit(true)
234    }
235    #[doc = r"Clears the field bit"]
236    #[inline(always)]
237    pub fn clear_bit(self) -> &'a mut W {
238        self.bit(false)
239    }
240    #[doc = r"Writes raw bits to the field"]
241    #[inline(always)]
242    pub fn bit(self, value: bool) -> &'a mut W {
243        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
244        self.w
245    }
246}
247#[doc = "Message Buffer Data Size for Region 0\n\nValue on reset: 0"]
248#[derive(Clone, Copy, Debug, PartialEq)]
249#[repr(u8)]
250pub enum MBDSR0_A {
251    #[doc = "0: Selects 8 bytes per Message Buffer."]
252    _00 = 0,
253    #[doc = "1: Selects 16 bytes per Message Buffer."]
254    _01 = 1,
255    #[doc = "2: Selects 32 bytes per Message Buffer."]
256    _10 = 2,
257    #[doc = "3: Selects 64 bytes per Message Buffer."]
258    _11 = 3,
259}
260impl From<MBDSR0_A> for u8 {
261    #[inline(always)]
262    fn from(variant: MBDSR0_A) -> Self {
263        variant as _
264    }
265}
266#[doc = "Field `MBDSR0` reader - Message Buffer Data Size for Region 0"]
267pub struct MBDSR0_R(crate::FieldReader<u8, MBDSR0_A>);
268impl MBDSR0_R {
269    #[inline(always)]
270    pub(crate) fn new(bits: u8) -> Self {
271        MBDSR0_R(crate::FieldReader::new(bits))
272    }
273    #[doc = r"Get enumerated values variant"]
274    #[inline(always)]
275    pub fn variant(&self) -> MBDSR0_A {
276        match self.bits {
277            0 => MBDSR0_A::_00,
278            1 => MBDSR0_A::_01,
279            2 => MBDSR0_A::_10,
280            3 => MBDSR0_A::_11,
281            _ => unreachable!(),
282        }
283    }
284    #[doc = "Checks if the value of the field is `_00`"]
285    #[inline(always)]
286    pub fn is_00(&self) -> bool {
287        **self == MBDSR0_A::_00
288    }
289    #[doc = "Checks if the value of the field is `_01`"]
290    #[inline(always)]
291    pub fn is_01(&self) -> bool {
292        **self == MBDSR0_A::_01
293    }
294    #[doc = "Checks if the value of the field is `_10`"]
295    #[inline(always)]
296    pub fn is_10(&self) -> bool {
297        **self == MBDSR0_A::_10
298    }
299    #[doc = "Checks if the value of the field is `_11`"]
300    #[inline(always)]
301    pub fn is_11(&self) -> bool {
302        **self == MBDSR0_A::_11
303    }
304}
305impl core::ops::Deref for MBDSR0_R {
306    type Target = crate::FieldReader<u8, MBDSR0_A>;
307    #[inline(always)]
308    fn deref(&self) -> &Self::Target {
309        &self.0
310    }
311}
312#[doc = "Field `MBDSR0` writer - Message Buffer Data Size for Region 0"]
313pub struct MBDSR0_W<'a> {
314    w: &'a mut W,
315}
316impl<'a> MBDSR0_W<'a> {
317    #[doc = r"Writes `variant` to the field"]
318    #[inline(always)]
319    pub fn variant(self, variant: MBDSR0_A) -> &'a mut W {
320        self.bits(variant.into())
321    }
322    #[doc = "Selects 8 bytes per Message Buffer."]
323    #[inline(always)]
324    pub fn _00(self) -> &'a mut W {
325        self.variant(MBDSR0_A::_00)
326    }
327    #[doc = "Selects 16 bytes per Message Buffer."]
328    #[inline(always)]
329    pub fn _01(self) -> &'a mut W {
330        self.variant(MBDSR0_A::_01)
331    }
332    #[doc = "Selects 32 bytes per Message Buffer."]
333    #[inline(always)]
334    pub fn _10(self) -> &'a mut W {
335        self.variant(MBDSR0_A::_10)
336    }
337    #[doc = "Selects 64 bytes per Message Buffer."]
338    #[inline(always)]
339    pub fn _11(self) -> &'a mut W {
340        self.variant(MBDSR0_A::_11)
341    }
342    #[doc = r"Writes raw bits to the field"]
343    #[inline(always)]
344    pub fn bits(self, value: u8) -> &'a mut W {
345        self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16);
346        self.w
347    }
348}
349#[doc = "Bit Rate Switch Enable\n\nValue on reset: 1"]
350#[derive(Clone, Copy, Debug, PartialEq)]
351pub enum FDRATE_A {
352    #[doc = "0: Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
353    _0 = 0,
354    #[doc = "1: Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
355    _1 = 1,
356}
357impl From<FDRATE_A> for bool {
358    #[inline(always)]
359    fn from(variant: FDRATE_A) -> Self {
360        variant as u8 != 0
361    }
362}
363#[doc = "Field `FDRATE` reader - Bit Rate Switch Enable"]
364pub struct FDRATE_R(crate::FieldReader<bool, FDRATE_A>);
365impl FDRATE_R {
366    #[inline(always)]
367    pub(crate) fn new(bits: bool) -> Self {
368        FDRATE_R(crate::FieldReader::new(bits))
369    }
370    #[doc = r"Get enumerated values variant"]
371    #[inline(always)]
372    pub fn variant(&self) -> FDRATE_A {
373        match self.bits {
374            false => FDRATE_A::_0,
375            true => FDRATE_A::_1,
376        }
377    }
378    #[doc = "Checks if the value of the field is `_0`"]
379    #[inline(always)]
380    pub fn is_0(&self) -> bool {
381        **self == FDRATE_A::_0
382    }
383    #[doc = "Checks if the value of the field is `_1`"]
384    #[inline(always)]
385    pub fn is_1(&self) -> bool {
386        **self == FDRATE_A::_1
387    }
388}
389impl core::ops::Deref for FDRATE_R {
390    type Target = crate::FieldReader<bool, FDRATE_A>;
391    #[inline(always)]
392    fn deref(&self) -> &Self::Target {
393        &self.0
394    }
395}
396#[doc = "Field `FDRATE` writer - Bit Rate Switch Enable"]
397pub struct FDRATE_W<'a> {
398    w: &'a mut W,
399}
400impl<'a> FDRATE_W<'a> {
401    #[doc = r"Writes `variant` to the field"]
402    #[inline(always)]
403    pub fn variant(self, variant: FDRATE_A) -> &'a mut W {
404        self.bit(variant.into())
405    }
406    #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
407    #[inline(always)]
408    pub fn _0(self) -> &'a mut W {
409        self.variant(FDRATE_A::_0)
410    }
411    #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
412    #[inline(always)]
413    pub fn _1(self) -> &'a mut W {
414        self.variant(FDRATE_A::_1)
415    }
416    #[doc = r"Sets the field bit"]
417    #[inline(always)]
418    pub fn set_bit(self) -> &'a mut W {
419        self.bit(true)
420    }
421    #[doc = r"Clears the field bit"]
422    #[inline(always)]
423    pub fn clear_bit(self) -> &'a mut W {
424        self.bit(false)
425    }
426    #[doc = r"Writes raw bits to the field"]
427    #[inline(always)]
428    pub fn bit(self, value: bool) -> &'a mut W {
429        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
430        self.w
431    }
432}
433impl R {
434    #[doc = "Bits 0:5 - Transceiver Delay Compensation Value"]
435    #[inline(always)]
436    pub fn tdcval(&self) -> TDCVAL_R {
437        TDCVAL_R::new((self.bits & 0x3f) as u8)
438    }
439    #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
440    #[inline(always)]
441    pub fn tdcoff(&self) -> TDCOFF_R {
442        TDCOFF_R::new(((self.bits >> 8) & 0x1f) as u8)
443    }
444    #[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
445    #[inline(always)]
446    pub fn tdcfail(&self) -> TDCFAIL_R {
447        TDCFAIL_R::new(((self.bits >> 14) & 0x01) != 0)
448    }
449    #[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
450    #[inline(always)]
451    pub fn tdcen(&self) -> TDCEN_R {
452        TDCEN_R::new(((self.bits >> 15) & 0x01) != 0)
453    }
454    #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
455    #[inline(always)]
456    pub fn mbdsr0(&self) -> MBDSR0_R {
457        MBDSR0_R::new(((self.bits >> 16) & 0x03) as u8)
458    }
459    #[doc = "Bit 31 - Bit Rate Switch Enable"]
460    #[inline(always)]
461    pub fn fdrate(&self) -> FDRATE_R {
462        FDRATE_R::new(((self.bits >> 31) & 0x01) != 0)
463    }
464}
465impl W {
466    #[doc = "Bits 8:12 - Transceiver Delay Compensation Offset"]
467    #[inline(always)]
468    pub fn tdcoff(&mut self) -> TDCOFF_W {
469        TDCOFF_W { w: self }
470    }
471    #[doc = "Bit 14 - Transceiver Delay Compensation Fail"]
472    #[inline(always)]
473    pub fn tdcfail(&mut self) -> TDCFAIL_W {
474        TDCFAIL_W { w: self }
475    }
476    #[doc = "Bit 15 - Transceiver Delay Compensation Enable"]
477    #[inline(always)]
478    pub fn tdcen(&mut self) -> TDCEN_W {
479        TDCEN_W { w: self }
480    }
481    #[doc = "Bits 16:17 - Message Buffer Data Size for Region 0"]
482    #[inline(always)]
483    pub fn mbdsr0(&mut self) -> MBDSR0_W {
484        MBDSR0_W { w: self }
485    }
486    #[doc = "Bit 31 - Bit Rate Switch Enable"]
487    #[inline(always)]
488    pub fn fdrate(&mut self) -> FDRATE_W {
489        FDRATE_W { w: self }
490    }
491    #[doc = "Writes raw bits to the register."]
492    #[inline(always)]
493    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
494        self.0.bits(bits);
495        self
496    }
497}
498#[doc = "CAN FD Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fdctrl](index.html) module"]
499pub struct FDCTRL_SPEC;
500impl crate::RegisterSpec for FDCTRL_SPEC {
501    type Ux = u32;
502}
503#[doc = "`read()` method returns [fdctrl::R](R) reader structure"]
504impl crate::Readable for FDCTRL_SPEC {
505    type Reader = R;
506}
507#[doc = "`write(|w| ..)` method takes [fdctrl::W](W) writer structure"]
508impl crate::Writable for FDCTRL_SPEC {
509    type Writer = W;
510}
511#[doc = "`reset()` method sets FDCTRL to value 0x8000_0100"]
512impl crate::Resettable for FDCTRL_SPEC {
513    #[inline(always)]
514    fn reset_value() -> Self::Ux {
515        0x8000_0100
516    }
517}
s32k116_pac/can0/fdctrl.rs

s32k116_pac/can0/
fdctrl.rs
