Module s2pac_ch32v103::dma
source · Expand description
DMA controller
Modules§
- DMA channel configuration register (DMA_CFGR)
- DMA channel configuration register (DMA_CFGR)
- DMA channel configuration register (DMA_CFGR)
- DMA channel configuration register (DMA_CFGR)
- DMA channel configuration register (DMA_CFGR)
- DMA channel configuration register (DMA_CFGR)
- DMA channel configuration register (DMA_CFGR)
- DMA channel 1 number of data register
- DMA channel 2 number of data register
- DMA channel 3 number of data register
- DMA channel 4 number of data register
- DMA channel 5 number of data register
- DMA channel 6 number of data register
- DMA channel 7 number of data register
- DMA interrupt flag clear register (DMA_INTFCR)
- DMA interrupt status register (DMA_INTFR)
- DMA channel 1 memory address register
- DMA channel 2 memory address register
- DMA channel 3 memory address register
- DMA channel 4 memory address register
- DMA channel 5 memory address register
- DMA channel 6 memory address register
- DMA channel 7 memory address register
- DMA channel 1 peripheral address register
- DMA channel 2 peripheral address register
- DMA channel 3 peripheral address register
- DMA channel 4 peripheral address register
- DMA channel 5 peripheral address register
- DMA channel 6 peripheral address register
- DMA channel 7 peripheral address register
Structs§
- Register block
Type Aliases§
- CFGR1 (rw) register accessor: DMA channel configuration register (DMA_CFGR)
- CFGR2 (rw) register accessor: DMA channel configuration register (DMA_CFGR)
- CFGR3 (rw) register accessor: DMA channel configuration register (DMA_CFGR)
- CFGR4 (rw) register accessor: DMA channel configuration register (DMA_CFGR)
- CFGR5 (rw) register accessor: DMA channel configuration register (DMA_CFGR)
- CFGR6 (rw) register accessor: DMA channel configuration register (DMA_CFGR)
- CFGR7 (rw) register accessor: DMA channel configuration register (DMA_CFGR)
- CNTR1 (rw) register accessor: DMA channel 1 number of data register
- CNTR2 (rw) register accessor: DMA channel 2 number of data register
- CNTR3 (rw) register accessor: DMA channel 3 number of data register
- CNTR4 (rw) register accessor: DMA channel 4 number of data register
- CNTR5 (rw) register accessor: DMA channel 5 number of data register
- CNTR6 (rw) register accessor: DMA channel 6 number of data register
- CNTR7 (rw) register accessor: DMA channel 7 number of data register
- INTFCR (w) register accessor: DMA interrupt flag clear register (DMA_INTFCR)
- INTFR (r) register accessor: DMA interrupt status register (DMA_INTFR)
- MADDR1 (rw) register accessor: DMA channel 1 memory address register
- MADDR2 (rw) register accessor: DMA channel 2 memory address register
- MADDR3 (rw) register accessor: DMA channel 3 memory address register
- MADDR4 (rw) register accessor: DMA channel 4 memory address register
- MADDR5 (rw) register accessor: DMA channel 5 memory address register
- MADDR6 (rw) register accessor: DMA channel 6 memory address register
- MADDR7 (rw) register accessor: DMA channel 7 memory address register
- PADDR1 (rw) register accessor: DMA channel 1 peripheral address register
- PADDR2 (rw) register accessor: DMA channel 2 peripheral address register
- PADDR3 (rw) register accessor: DMA channel 3 peripheral address register
- PADDR4 (rw) register accessor: DMA channel 4 peripheral address register
- PADDR5 (rw) register accessor: DMA channel 5 peripheral address register
- PADDR6 (rw) register accessor: DMA channel 6 peripheral address register
- PADDR7 (rw) register accessor: DMA channel 7 peripheral address register