[−][src]Struct rysk_core::csr::Csr
The Control Status Registers (CSR) a single HART must provide storage for to comply with the privileged ISA Other CSR's may not need storage and as such are not a part of this struct
Fields
mhartid: R
The ID of this hart
mtvec: R
The address of a potentially vectorised interupt handler
medeleg: R
Delegation of exceptions to lower modes
mideleg: R
Delegation of interrupts to lower modes
mie: R
Sets if interrupts are enabled
mip: R
States if an interrupt is pending
mcycle: Register64
Counts the number of cycles the hart has executed. As there is no speculative execution or other operations minstret is the same as this value
mcounteren: Register32
Determine if counters are accessible in lower privilege modes
mscratch: R
Scratch register dedicated to machine-mode usage
mepc: R
The virtual address of an interrupted or excepted instruction in machine-mode
mcause: R
The cause of an interrupt or exception
mtval: R
An implementation-defined value set during a trap
Implementations
impl<R: Register> Csr<R>
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Auto Trait Implementations
impl<R> RefUnwindSafe for Csr<R> where
R: RefUnwindSafe,
R: RefUnwindSafe,
impl<R> Send for Csr<R> where
R: Send,
R: Send,
impl<R> Sync for Csr<R> where
R: Sync,
R: Sync,
impl<R> Unpin for Csr<R> where
R: Unpin,
R: Unpin,
impl<R> UnwindSafe for Csr<R> where
R: UnwindSafe,
R: UnwindSafe,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,