Constant rvemu::devices::uart_cli::UART_LSR

pub const UART_LSR: usize = UART_BASE + 5; // 268_435_461usize

Line status register. LSR BIT 1: 0 = no overrun error (normal) 1 = overrun error. A character arived before receive holding register was emptied or if FIFOs are enabled, an overrun error will occur only after the FIFO is full and the next character has been completely received in the shift register. Note that character in the shift register is overwritten, but it is not transferred to the FIFO. LSR BIT 6: 0 = transmitter holding and shift registers are full. 1 = transmit holding register is empty. In FIFO mode this bit is set to one whenever the the transmitter FIFO and transmit shift register are empty.