rv32m1_ri5cy_pac/rtc/
lr.rs

1#[doc = "Reader of register LR"]
2pub type R = crate::R<u32, super::LR>;
3#[doc = "Writer for register LR"]
4pub type W = crate::W<u32, super::LR>;
5#[doc = "Register LR `reset()`'s with value 0x000f_ffff"]
6impl crate::ResetValue for super::LR {
7  type Type = u32;
8  #[inline(always)]
9  fn reset_value() -> Self::Type {
10    0x000f_ffff
11  }
12}
13#[doc = "Time Compensation Lock\n\nValue on reset: 1"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum TCL_A {
16  #[doc = "0: Time Compensation Register is locked and writes are ignored."]
17  TCL_0,
18  #[doc = "1: Time Compensation Register is not locked and writes complete as normal."]
19  TCL_1,
20}
21impl From<TCL_A> for bool {
22  #[inline(always)]
23  fn from(variant: TCL_A) -> Self {
24    match variant {
25      TCL_A::TCL_0 => false,
26      TCL_A::TCL_1 => true,
27    }
28  }
29}
30#[doc = "Reader of field `TCL`"]
31pub type TCL_R = crate::R<bool, TCL_A>;
32impl TCL_R {
33  #[doc = r"Get enumerated values variant"]
34  #[inline(always)]
35  pub fn variant(&self) -> TCL_A {
36    match self.bits {
37      false => TCL_A::TCL_0,
38      true => TCL_A::TCL_1,
39    }
40  }
41  #[doc = "Checks if the value of the field is `TCL_0`"]
42  #[inline(always)]
43  pub fn is_tcl_0(&self) -> bool {
44    *self == TCL_A::TCL_0
45  }
46  #[doc = "Checks if the value of the field is `TCL_1`"]
47  #[inline(always)]
48  pub fn is_tcl_1(&self) -> bool {
49    *self == TCL_A::TCL_1
50  }
51}
52#[doc = "Write proxy for field `TCL`"]
53pub struct TCL_W<'a> {
54  w: &'a mut W,
55}
56impl<'a> TCL_W<'a> {
57  #[doc = r"Writes `variant` to the field"]
58  #[inline(always)]
59  pub fn variant(self, variant: TCL_A) -> &'a mut W {
60    {
61      self.bit(variant.into())
62    }
63  }
64  #[doc = "Time Compensation Register is locked and writes are ignored."]
65  #[inline(always)]
66  pub fn tcl_0(self) -> &'a mut W {
67    self.variant(TCL_A::TCL_0)
68  }
69  #[doc = "Time Compensation Register is not locked and writes complete as normal."]
70  #[inline(always)]
71  pub fn tcl_1(self) -> &'a mut W {
72    self.variant(TCL_A::TCL_1)
73  }
74  #[doc = r"Sets the field bit"]
75  #[inline(always)]
76  pub fn set_bit(self) -> &'a mut W {
77    self.bit(true)
78  }
79  #[doc = r"Clears the field bit"]
80  #[inline(always)]
81  pub fn clear_bit(self) -> &'a mut W {
82    self.bit(false)
83  }
84  #[doc = r"Writes raw bits to the field"]
85  #[inline(always)]
86  pub fn bit(self, value: bool) -> &'a mut W {
87    self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
88    self.w
89  }
90}
91#[doc = "Control Register Lock\n\nValue on reset: 1"]
92#[derive(Clone, Copy, Debug, PartialEq)]
93pub enum CRL_A {
94  #[doc = "0: Control Register is locked and writes are ignored."]
95  CRL_0,
96  #[doc = "1: Control Register is not locked and writes complete as normal."]
97  CRL_1,
98}
99impl From<CRL_A> for bool {
100  #[inline(always)]
101  fn from(variant: CRL_A) -> Self {
102    match variant {
103      CRL_A::CRL_0 => false,
104      CRL_A::CRL_1 => true,
105    }
106  }
107}
108#[doc = "Reader of field `CRL`"]
109pub type CRL_R = crate::R<bool, CRL_A>;
110impl CRL_R {
111  #[doc = r"Get enumerated values variant"]
112  #[inline(always)]
113  pub fn variant(&self) -> CRL_A {
114    match self.bits {
115      false => CRL_A::CRL_0,
116      true => CRL_A::CRL_1,
117    }
118  }
119  #[doc = "Checks if the value of the field is `CRL_0`"]
120  #[inline(always)]
121  pub fn is_crl_0(&self) -> bool {
122    *self == CRL_A::CRL_0
123  }
124  #[doc = "Checks if the value of the field is `CRL_1`"]
125  #[inline(always)]
126  pub fn is_crl_1(&self) -> bool {
127    *self == CRL_A::CRL_1
128  }
129}
130#[doc = "Write proxy for field `CRL`"]
131pub struct CRL_W<'a> {
132  w: &'a mut W,
133}
134impl<'a> CRL_W<'a> {
135  #[doc = r"Writes `variant` to the field"]
136  #[inline(always)]
137  pub fn variant(self, variant: CRL_A) -> &'a mut W {
138    {
139      self.bit(variant.into())
140    }
141  }
142  #[doc = "Control Register is locked and writes are ignored."]
143  #[inline(always)]
144  pub fn crl_0(self) -> &'a mut W {
145    self.variant(CRL_A::CRL_0)
146  }
147  #[doc = "Control Register is not locked and writes complete as normal."]
148  #[inline(always)]
149  pub fn crl_1(self) -> &'a mut W {
150    self.variant(CRL_A::CRL_1)
151  }
152  #[doc = r"Sets the field bit"]
153  #[inline(always)]
154  pub fn set_bit(self) -> &'a mut W {
155    self.bit(true)
156  }
157  #[doc = r"Clears the field bit"]
158  #[inline(always)]
159  pub fn clear_bit(self) -> &'a mut W {
160    self.bit(false)
161  }
162  #[doc = r"Writes raw bits to the field"]
163  #[inline(always)]
164  pub fn bit(self, value: bool) -> &'a mut W {
165    self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
166    self.w
167  }
168}
169#[doc = "Status Register Lock\n\nValue on reset: 1"]
170#[derive(Clone, Copy, Debug, PartialEq)]
171pub enum SRL_A {
172  #[doc = "0: Status Register is locked and writes are ignored."]
173  SRL_0,
174  #[doc = "1: Status Register is not locked and writes complete as normal."]
175  SRL_1,
176}
177impl From<SRL_A> for bool {
178  #[inline(always)]
179  fn from(variant: SRL_A) -> Self {
180    match variant {
181      SRL_A::SRL_0 => false,
182      SRL_A::SRL_1 => true,
183    }
184  }
185}
186#[doc = "Reader of field `SRL`"]
187pub type SRL_R = crate::R<bool, SRL_A>;
188impl SRL_R {
189  #[doc = r"Get enumerated values variant"]
190  #[inline(always)]
191  pub fn variant(&self) -> SRL_A {
192    match self.bits {
193      false => SRL_A::SRL_0,
194      true => SRL_A::SRL_1,
195    }
196  }
197  #[doc = "Checks if the value of the field is `SRL_0`"]
198  #[inline(always)]
199  pub fn is_srl_0(&self) -> bool {
200    *self == SRL_A::SRL_0
201  }
202  #[doc = "Checks if the value of the field is `SRL_1`"]
203  #[inline(always)]
204  pub fn is_srl_1(&self) -> bool {
205    *self == SRL_A::SRL_1
206  }
207}
208#[doc = "Write proxy for field `SRL`"]
209pub struct SRL_W<'a> {
210  w: &'a mut W,
211}
212impl<'a> SRL_W<'a> {
213  #[doc = r"Writes `variant` to the field"]
214  #[inline(always)]
215  pub fn variant(self, variant: SRL_A) -> &'a mut W {
216    {
217      self.bit(variant.into())
218    }
219  }
220  #[doc = "Status Register is locked and writes are ignored."]
221  #[inline(always)]
222  pub fn srl_0(self) -> &'a mut W {
223    self.variant(SRL_A::SRL_0)
224  }
225  #[doc = "Status Register is not locked and writes complete as normal."]
226  #[inline(always)]
227  pub fn srl_1(self) -> &'a mut W {
228    self.variant(SRL_A::SRL_1)
229  }
230  #[doc = r"Sets the field bit"]
231  #[inline(always)]
232  pub fn set_bit(self) -> &'a mut W {
233    self.bit(true)
234  }
235  #[doc = r"Clears the field bit"]
236  #[inline(always)]
237  pub fn clear_bit(self) -> &'a mut W {
238    self.bit(false)
239  }
240  #[doc = r"Writes raw bits to the field"]
241  #[inline(always)]
242  pub fn bit(self, value: bool) -> &'a mut W {
243    self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
244    self.w
245  }
246}
247#[doc = "Lock Register Lock\n\nValue on reset: 1"]
248#[derive(Clone, Copy, Debug, PartialEq)]
249pub enum LRL_A {
250  #[doc = "0: Lock Register is locked and writes are ignored."]
251  LRL_0,
252  #[doc = "1: Lock Register is not locked and writes complete as normal."]
253  LRL_1,
254}
255impl From<LRL_A> for bool {
256  #[inline(always)]
257  fn from(variant: LRL_A) -> Self {
258    match variant {
259      LRL_A::LRL_0 => false,
260      LRL_A::LRL_1 => true,
261    }
262  }
263}
264#[doc = "Reader of field `LRL`"]
265pub type LRL_R = crate::R<bool, LRL_A>;
266impl LRL_R {
267  #[doc = r"Get enumerated values variant"]
268  #[inline(always)]
269  pub fn variant(&self) -> LRL_A {
270    match self.bits {
271      false => LRL_A::LRL_0,
272      true => LRL_A::LRL_1,
273    }
274  }
275  #[doc = "Checks if the value of the field is `LRL_0`"]
276  #[inline(always)]
277  pub fn is_lrl_0(&self) -> bool {
278    *self == LRL_A::LRL_0
279  }
280  #[doc = "Checks if the value of the field is `LRL_1`"]
281  #[inline(always)]
282  pub fn is_lrl_1(&self) -> bool {
283    *self == LRL_A::LRL_1
284  }
285}
286#[doc = "Write proxy for field `LRL`"]
287pub struct LRL_W<'a> {
288  w: &'a mut W,
289}
290impl<'a> LRL_W<'a> {
291  #[doc = r"Writes `variant` to the field"]
292  #[inline(always)]
293  pub fn variant(self, variant: LRL_A) -> &'a mut W {
294    {
295      self.bit(variant.into())
296    }
297  }
298  #[doc = "Lock Register is locked and writes are ignored."]
299  #[inline(always)]
300  pub fn lrl_0(self) -> &'a mut W {
301    self.variant(LRL_A::LRL_0)
302  }
303  #[doc = "Lock Register is not locked and writes complete as normal."]
304  #[inline(always)]
305  pub fn lrl_1(self) -> &'a mut W {
306    self.variant(LRL_A::LRL_1)
307  }
308  #[doc = r"Sets the field bit"]
309  #[inline(always)]
310  pub fn set_bit(self) -> &'a mut W {
311    self.bit(true)
312  }
313  #[doc = r"Clears the field bit"]
314  #[inline(always)]
315  pub fn clear_bit(self) -> &'a mut W {
316    self.bit(false)
317  }
318  #[doc = r"Writes raw bits to the field"]
319  #[inline(always)]
320  pub fn bit(self, value: bool) -> &'a mut W {
321    self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
322    self.w
323  }
324}
325#[doc = "Tamper Time Seconds Lock\n\nValue on reset: 1"]
326#[derive(Clone, Copy, Debug, PartialEq)]
327pub enum TTSL_A {
328  #[doc = "0: Tamper Time Seconds Register is locked and writes are ignored."]
329  TTSL_0,
330  #[doc = "1: Tamper Time Seconds Register is not locked and writes complete as normal."]
331  TTSL_1,
332}
333impl From<TTSL_A> for bool {
334  #[inline(always)]
335  fn from(variant: TTSL_A) -> Self {
336    match variant {
337      TTSL_A::TTSL_0 => false,
338      TTSL_A::TTSL_1 => true,
339    }
340  }
341}
342#[doc = "Reader of field `TTSL`"]
343pub type TTSL_R = crate::R<bool, TTSL_A>;
344impl TTSL_R {
345  #[doc = r"Get enumerated values variant"]
346  #[inline(always)]
347  pub fn variant(&self) -> TTSL_A {
348    match self.bits {
349      false => TTSL_A::TTSL_0,
350      true => TTSL_A::TTSL_1,
351    }
352  }
353  #[doc = "Checks if the value of the field is `TTSL_0`"]
354  #[inline(always)]
355  pub fn is_ttsl_0(&self) -> bool {
356    *self == TTSL_A::TTSL_0
357  }
358  #[doc = "Checks if the value of the field is `TTSL_1`"]
359  #[inline(always)]
360  pub fn is_ttsl_1(&self) -> bool {
361    *self == TTSL_A::TTSL_1
362  }
363}
364#[doc = "Write proxy for field `TTSL`"]
365pub struct TTSL_W<'a> {
366  w: &'a mut W,
367}
368impl<'a> TTSL_W<'a> {
369  #[doc = r"Writes `variant` to the field"]
370  #[inline(always)]
371  pub fn variant(self, variant: TTSL_A) -> &'a mut W {
372    {
373      self.bit(variant.into())
374    }
375  }
376  #[doc = "Tamper Time Seconds Register is locked and writes are ignored."]
377  #[inline(always)]
378  pub fn ttsl_0(self) -> &'a mut W {
379    self.variant(TTSL_A::TTSL_0)
380  }
381  #[doc = "Tamper Time Seconds Register is not locked and writes complete as normal."]
382  #[inline(always)]
383  pub fn ttsl_1(self) -> &'a mut W {
384    self.variant(TTSL_A::TTSL_1)
385  }
386  #[doc = r"Sets the field bit"]
387  #[inline(always)]
388  pub fn set_bit(self) -> &'a mut W {
389    self.bit(true)
390  }
391  #[doc = r"Clears the field bit"]
392  #[inline(always)]
393  pub fn clear_bit(self) -> &'a mut W {
394    self.bit(false)
395  }
396  #[doc = r"Writes raw bits to the field"]
397  #[inline(always)]
398  pub fn bit(self, value: bool) -> &'a mut W {
399    self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
400    self.w
401  }
402}
403#[doc = "Monotonic Enable Lock\n\nValue on reset: 1"]
404#[derive(Clone, Copy, Debug, PartialEq)]
405pub enum MEL_A {
406  #[doc = "0: Monotonic Enable Register is locked and writes are ignored."]
407  MEL_0,
408  #[doc = "1: Monotonic Enable Register is not locked and writes complete as normal."]
409  MEL_1,
410}
411impl From<MEL_A> for bool {
412  #[inline(always)]
413  fn from(variant: MEL_A) -> Self {
414    match variant {
415      MEL_A::MEL_0 => false,
416      MEL_A::MEL_1 => true,
417    }
418  }
419}
420#[doc = "Reader of field `MEL`"]
421pub type MEL_R = crate::R<bool, MEL_A>;
422impl MEL_R {
423  #[doc = r"Get enumerated values variant"]
424  #[inline(always)]
425  pub fn variant(&self) -> MEL_A {
426    match self.bits {
427      false => MEL_A::MEL_0,
428      true => MEL_A::MEL_1,
429    }
430  }
431  #[doc = "Checks if the value of the field is `MEL_0`"]
432  #[inline(always)]
433  pub fn is_mel_0(&self) -> bool {
434    *self == MEL_A::MEL_0
435  }
436  #[doc = "Checks if the value of the field is `MEL_1`"]
437  #[inline(always)]
438  pub fn is_mel_1(&self) -> bool {
439    *self == MEL_A::MEL_1
440  }
441}
442#[doc = "Write proxy for field `MEL`"]
443pub struct MEL_W<'a> {
444  w: &'a mut W,
445}
446impl<'a> MEL_W<'a> {
447  #[doc = r"Writes `variant` to the field"]
448  #[inline(always)]
449  pub fn variant(self, variant: MEL_A) -> &'a mut W {
450    {
451      self.bit(variant.into())
452    }
453  }
454  #[doc = "Monotonic Enable Register is locked and writes are ignored."]
455  #[inline(always)]
456  pub fn mel_0(self) -> &'a mut W {
457    self.variant(MEL_A::MEL_0)
458  }
459  #[doc = "Monotonic Enable Register is not locked and writes complete as normal."]
460  #[inline(always)]
461  pub fn mel_1(self) -> &'a mut W {
462    self.variant(MEL_A::MEL_1)
463  }
464  #[doc = r"Sets the field bit"]
465  #[inline(always)]
466  pub fn set_bit(self) -> &'a mut W {
467    self.bit(true)
468  }
469  #[doc = r"Clears the field bit"]
470  #[inline(always)]
471  pub fn clear_bit(self) -> &'a mut W {
472    self.bit(false)
473  }
474  #[doc = r"Writes raw bits to the field"]
475  #[inline(always)]
476  pub fn bit(self, value: bool) -> &'a mut W {
477    self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
478    self.w
479  }
480}
481#[doc = "Monotonic Counter Low Lock\n\nValue on reset: 1"]
482#[derive(Clone, Copy, Debug, PartialEq)]
483pub enum MCLL_A {
484  #[doc = "0: Monotonic Counter Low Register is locked and writes are ignored."]
485  MCLL_0,
486  #[doc = "1: Monotonic Counter Low Register is not locked and writes complete as normal."]
487  MCLL_1,
488}
489impl From<MCLL_A> for bool {
490  #[inline(always)]
491  fn from(variant: MCLL_A) -> Self {
492    match variant {
493      MCLL_A::MCLL_0 => false,
494      MCLL_A::MCLL_1 => true,
495    }
496  }
497}
498#[doc = "Reader of field `MCLL`"]
499pub type MCLL_R = crate::R<bool, MCLL_A>;
500impl MCLL_R {
501  #[doc = r"Get enumerated values variant"]
502  #[inline(always)]
503  pub fn variant(&self) -> MCLL_A {
504    match self.bits {
505      false => MCLL_A::MCLL_0,
506      true => MCLL_A::MCLL_1,
507    }
508  }
509  #[doc = "Checks if the value of the field is `MCLL_0`"]
510  #[inline(always)]
511  pub fn is_mcll_0(&self) -> bool {
512    *self == MCLL_A::MCLL_0
513  }
514  #[doc = "Checks if the value of the field is `MCLL_1`"]
515  #[inline(always)]
516  pub fn is_mcll_1(&self) -> bool {
517    *self == MCLL_A::MCLL_1
518  }
519}
520#[doc = "Write proxy for field `MCLL`"]
521pub struct MCLL_W<'a> {
522  w: &'a mut W,
523}
524impl<'a> MCLL_W<'a> {
525  #[doc = r"Writes `variant` to the field"]
526  #[inline(always)]
527  pub fn variant(self, variant: MCLL_A) -> &'a mut W {
528    {
529      self.bit(variant.into())
530    }
531  }
532  #[doc = "Monotonic Counter Low Register is locked and writes are ignored."]
533  #[inline(always)]
534  pub fn mcll_0(self) -> &'a mut W {
535    self.variant(MCLL_A::MCLL_0)
536  }
537  #[doc = "Monotonic Counter Low Register is not locked and writes complete as normal."]
538  #[inline(always)]
539  pub fn mcll_1(self) -> &'a mut W {
540    self.variant(MCLL_A::MCLL_1)
541  }
542  #[doc = r"Sets the field bit"]
543  #[inline(always)]
544  pub fn set_bit(self) -> &'a mut W {
545    self.bit(true)
546  }
547  #[doc = r"Clears the field bit"]
548  #[inline(always)]
549  pub fn clear_bit(self) -> &'a mut W {
550    self.bit(false)
551  }
552  #[doc = r"Writes raw bits to the field"]
553  #[inline(always)]
554  pub fn bit(self, value: bool) -> &'a mut W {
555    self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
556    self.w
557  }
558}
559#[doc = "Monotonic Counter High Lock\n\nValue on reset: 1"]
560#[derive(Clone, Copy, Debug, PartialEq)]
561pub enum MCHL_A {
562  #[doc = "0: Monotonic Counter High Register is locked and writes are ignored."]
563  MCHL_0,
564  #[doc = "1: Monotonic Counter High Register is not locked and writes complete as normal."]
565  MCHL_1,
566}
567impl From<MCHL_A> for bool {
568  #[inline(always)]
569  fn from(variant: MCHL_A) -> Self {
570    match variant {
571      MCHL_A::MCHL_0 => false,
572      MCHL_A::MCHL_1 => true,
573    }
574  }
575}
576#[doc = "Reader of field `MCHL`"]
577pub type MCHL_R = crate::R<bool, MCHL_A>;
578impl MCHL_R {
579  #[doc = r"Get enumerated values variant"]
580  #[inline(always)]
581  pub fn variant(&self) -> MCHL_A {
582    match self.bits {
583      false => MCHL_A::MCHL_0,
584      true => MCHL_A::MCHL_1,
585    }
586  }
587  #[doc = "Checks if the value of the field is `MCHL_0`"]
588  #[inline(always)]
589  pub fn is_mchl_0(&self) -> bool {
590    *self == MCHL_A::MCHL_0
591  }
592  #[doc = "Checks if the value of the field is `MCHL_1`"]
593  #[inline(always)]
594  pub fn is_mchl_1(&self) -> bool {
595    *self == MCHL_A::MCHL_1
596  }
597}
598#[doc = "Write proxy for field `MCHL`"]
599pub struct MCHL_W<'a> {
600  w: &'a mut W,
601}
602impl<'a> MCHL_W<'a> {
603  #[doc = r"Writes `variant` to the field"]
604  #[inline(always)]
605  pub fn variant(self, variant: MCHL_A) -> &'a mut W {
606    {
607      self.bit(variant.into())
608    }
609  }
610  #[doc = "Monotonic Counter High Register is locked and writes are ignored."]
611  #[inline(always)]
612  pub fn mchl_0(self) -> &'a mut W {
613    self.variant(MCHL_A::MCHL_0)
614  }
615  #[doc = "Monotonic Counter High Register is not locked and writes complete as normal."]
616  #[inline(always)]
617  pub fn mchl_1(self) -> &'a mut W {
618    self.variant(MCHL_A::MCHL_1)
619  }
620  #[doc = r"Sets the field bit"]
621  #[inline(always)]
622  pub fn set_bit(self) -> &'a mut W {
623    self.bit(true)
624  }
625  #[doc = r"Clears the field bit"]
626  #[inline(always)]
627  pub fn clear_bit(self) -> &'a mut W {
628    self.bit(false)
629  }
630  #[doc = r"Writes raw bits to the field"]
631  #[inline(always)]
632  pub fn bit(self, value: bool) -> &'a mut W {
633    self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
634    self.w
635  }
636}
637#[doc = "Tamper Detect Lock\n\nValue on reset: 1"]
638#[derive(Clone, Copy, Debug, PartialEq)]
639pub enum TDL_A {
640  #[doc = "0: Tamper Detect Register is locked and writes are ignored."]
641  TDL_0,
642  #[doc = "1: Tamper Detect Register is not locked and writes complete as normal."]
643  TDL_1,
644}
645impl From<TDL_A> for bool {
646  #[inline(always)]
647  fn from(variant: TDL_A) -> Self {
648    match variant {
649      TDL_A::TDL_0 => false,
650      TDL_A::TDL_1 => true,
651    }
652  }
653}
654#[doc = "Reader of field `TDL`"]
655pub type TDL_R = crate::R<bool, TDL_A>;
656impl TDL_R {
657  #[doc = r"Get enumerated values variant"]
658  #[inline(always)]
659  pub fn variant(&self) -> TDL_A {
660    match self.bits {
661      false => TDL_A::TDL_0,
662      true => TDL_A::TDL_1,
663    }
664  }
665  #[doc = "Checks if the value of the field is `TDL_0`"]
666  #[inline(always)]
667  pub fn is_tdl_0(&self) -> bool {
668    *self == TDL_A::TDL_0
669  }
670  #[doc = "Checks if the value of the field is `TDL_1`"]
671  #[inline(always)]
672  pub fn is_tdl_1(&self) -> bool {
673    *self == TDL_A::TDL_1
674  }
675}
676#[doc = "Write proxy for field `TDL`"]
677pub struct TDL_W<'a> {
678  w: &'a mut W,
679}
680impl<'a> TDL_W<'a> {
681  #[doc = r"Writes `variant` to the field"]
682  #[inline(always)]
683  pub fn variant(self, variant: TDL_A) -> &'a mut W {
684    {
685      self.bit(variant.into())
686    }
687  }
688  #[doc = "Tamper Detect Register is locked and writes are ignored."]
689  #[inline(always)]
690  pub fn tdl_0(self) -> &'a mut W {
691    self.variant(TDL_A::TDL_0)
692  }
693  #[doc = "Tamper Detect Register is not locked and writes complete as normal."]
694  #[inline(always)]
695  pub fn tdl_1(self) -> &'a mut W {
696    self.variant(TDL_A::TDL_1)
697  }
698  #[doc = r"Sets the field bit"]
699  #[inline(always)]
700  pub fn set_bit(self) -> &'a mut W {
701    self.bit(true)
702  }
703  #[doc = r"Clears the field bit"]
704  #[inline(always)]
705  pub fn clear_bit(self) -> &'a mut W {
706    self.bit(false)
707  }
708  #[doc = r"Writes raw bits to the field"]
709  #[inline(always)]
710  pub fn bit(self, value: bool) -> &'a mut W {
711    self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
712    self.w
713  }
714}
715#[doc = "Tamper Interrupt Lock\n\nValue on reset: 1"]
716#[derive(Clone, Copy, Debug, PartialEq)]
717pub enum TIL_A {
718  #[doc = "0: Tamper Interrupt Register is locked and writes are ignored."]
719  TIL_0,
720  #[doc = "1: Tamper Interrupt Register is not locked and writes complete as normal."]
721  TIL_1,
722}
723impl From<TIL_A> for bool {
724  #[inline(always)]
725  fn from(variant: TIL_A) -> Self {
726    match variant {
727      TIL_A::TIL_0 => false,
728      TIL_A::TIL_1 => true,
729    }
730  }
731}
732#[doc = "Reader of field `TIL`"]
733pub type TIL_R = crate::R<bool, TIL_A>;
734impl TIL_R {
735  #[doc = r"Get enumerated values variant"]
736  #[inline(always)]
737  pub fn variant(&self) -> TIL_A {
738    match self.bits {
739      false => TIL_A::TIL_0,
740      true => TIL_A::TIL_1,
741    }
742  }
743  #[doc = "Checks if the value of the field is `TIL_0`"]
744  #[inline(always)]
745  pub fn is_til_0(&self) -> bool {
746    *self == TIL_A::TIL_0
747  }
748  #[doc = "Checks if the value of the field is `TIL_1`"]
749  #[inline(always)]
750  pub fn is_til_1(&self) -> bool {
751    *self == TIL_A::TIL_1
752  }
753}
754#[doc = "Write proxy for field `TIL`"]
755pub struct TIL_W<'a> {
756  w: &'a mut W,
757}
758impl<'a> TIL_W<'a> {
759  #[doc = r"Writes `variant` to the field"]
760  #[inline(always)]
761  pub fn variant(self, variant: TIL_A) -> &'a mut W {
762    {
763      self.bit(variant.into())
764    }
765  }
766  #[doc = "Tamper Interrupt Register is locked and writes are ignored."]
767  #[inline(always)]
768  pub fn til_0(self) -> &'a mut W {
769    self.variant(TIL_A::TIL_0)
770  }
771  #[doc = "Tamper Interrupt Register is not locked and writes complete as normal."]
772  #[inline(always)]
773  pub fn til_1(self) -> &'a mut W {
774    self.variant(TIL_A::TIL_1)
775  }
776  #[doc = r"Sets the field bit"]
777  #[inline(always)]
778  pub fn set_bit(self) -> &'a mut W {
779    self.bit(true)
780  }
781  #[doc = r"Clears the field bit"]
782  #[inline(always)]
783  pub fn clear_bit(self) -> &'a mut W {
784    self.bit(false)
785  }
786  #[doc = r"Writes raw bits to the field"]
787  #[inline(always)]
788  pub fn bit(self, value: bool) -> &'a mut W {
789    self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
790    self.w
791  }
792}
793#[doc = "Reader of field `PCL`"]
794pub type PCL_R = crate::R<u8, u8>;
795#[doc = "Write proxy for field `PCL`"]
796pub struct PCL_W<'a> {
797  w: &'a mut W,
798}
799impl<'a> PCL_W<'a> {
800  #[doc = r"Writes raw bits to the field"]
801  #[inline(always)]
802  pub unsafe fn bits(self, value: u8) -> &'a mut W {
803    self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
804    self.w
805  }
806}
807impl R {
808  #[doc = "Bit 3 - Time Compensation Lock"]
809  #[inline(always)]
810  pub fn tcl(&self) -> TCL_R {
811    TCL_R::new(((self.bits >> 3) & 0x01) != 0)
812  }
813  #[doc = "Bit 4 - Control Register Lock"]
814  #[inline(always)]
815  pub fn crl(&self) -> CRL_R {
816    CRL_R::new(((self.bits >> 4) & 0x01) != 0)
817  }
818  #[doc = "Bit 5 - Status Register Lock"]
819  #[inline(always)]
820  pub fn srl(&self) -> SRL_R {
821    SRL_R::new(((self.bits >> 5) & 0x01) != 0)
822  }
823  #[doc = "Bit 6 - Lock Register Lock"]
824  #[inline(always)]
825  pub fn lrl(&self) -> LRL_R {
826    LRL_R::new(((self.bits >> 6) & 0x01) != 0)
827  }
828  #[doc = "Bit 8 - Tamper Time Seconds Lock"]
829  #[inline(always)]
830  pub fn ttsl(&self) -> TTSL_R {
831    TTSL_R::new(((self.bits >> 8) & 0x01) != 0)
832  }
833  #[doc = "Bit 9 - Monotonic Enable Lock"]
834  #[inline(always)]
835  pub fn mel(&self) -> MEL_R {
836    MEL_R::new(((self.bits >> 9) & 0x01) != 0)
837  }
838  #[doc = "Bit 10 - Monotonic Counter Low Lock"]
839  #[inline(always)]
840  pub fn mcll(&self) -> MCLL_R {
841    MCLL_R::new(((self.bits >> 10) & 0x01) != 0)
842  }
843  #[doc = "Bit 11 - Monotonic Counter High Lock"]
844  #[inline(always)]
845  pub fn mchl(&self) -> MCHL_R {
846    MCHL_R::new(((self.bits >> 11) & 0x01) != 0)
847  }
848  #[doc = "Bit 13 - Tamper Detect Lock"]
849  #[inline(always)]
850  pub fn tdl(&self) -> TDL_R {
851    TDL_R::new(((self.bits >> 13) & 0x01) != 0)
852  }
853  #[doc = "Bit 15 - Tamper Interrupt Lock"]
854  #[inline(always)]
855  pub fn til(&self) -> TIL_R {
856    TIL_R::new(((self.bits >> 15) & 0x01) != 0)
857  }
858  #[doc = "Bits 16:19 - Pin Configuration Lock"]
859  #[inline(always)]
860  pub fn pcl(&self) -> PCL_R {
861    PCL_R::new(((self.bits >> 16) & 0x0f) as u8)
862  }
863}
864impl W {
865  #[doc = "Bit 3 - Time Compensation Lock"]
866  #[inline(always)]
867  pub fn tcl(&mut self) -> TCL_W {
868    TCL_W { w: self }
869  }
870  #[doc = "Bit 4 - Control Register Lock"]
871  #[inline(always)]
872  pub fn crl(&mut self) -> CRL_W {
873    CRL_W { w: self }
874  }
875  #[doc = "Bit 5 - Status Register Lock"]
876  #[inline(always)]
877  pub fn srl(&mut self) -> SRL_W {
878    SRL_W { w: self }
879  }
880  #[doc = "Bit 6 - Lock Register Lock"]
881  #[inline(always)]
882  pub fn lrl(&mut self) -> LRL_W {
883    LRL_W { w: self }
884  }
885  #[doc = "Bit 8 - Tamper Time Seconds Lock"]
886  #[inline(always)]
887  pub fn ttsl(&mut self) -> TTSL_W {
888    TTSL_W { w: self }
889  }
890  #[doc = "Bit 9 - Monotonic Enable Lock"]
891  #[inline(always)]
892  pub fn mel(&mut self) -> MEL_W {
893    MEL_W { w: self }
894  }
895  #[doc = "Bit 10 - Monotonic Counter Low Lock"]
896  #[inline(always)]
897  pub fn mcll(&mut self) -> MCLL_W {
898    MCLL_W { w: self }
899  }
900  #[doc = "Bit 11 - Monotonic Counter High Lock"]
901  #[inline(always)]
902  pub fn mchl(&mut self) -> MCHL_W {
903    MCHL_W { w: self }
904  }
905  #[doc = "Bit 13 - Tamper Detect Lock"]
906  #[inline(always)]
907  pub fn tdl(&mut self) -> TDL_W {
908    TDL_W { w: self }
909  }
910  #[doc = "Bit 15 - Tamper Interrupt Lock"]
911  #[inline(always)]
912  pub fn til(&mut self) -> TIL_W {
913    TIL_W { w: self }
914  }
915  #[doc = "Bits 16:19 - Pin Configuration Lock"]
916  #[inline(always)]
917  pub fn pcl(&mut self) -> PCL_W {
918    PCL_W { w: self }
919  }
920}
rv32m1_ri5cy_pac/rtc/lr.rs

rv32m1_ri5cy_pac/rtc/
lr.rs
