[−][src]Module rv32m1_ri5cy_pac::scg::csr
Clock Status Register
Enums
| DIVBUS_A | Bus Clock Divide Ratio |
| DIVCORE_A | Core Clock Divide Ratio |
| DIVEXT_A | External Clock Divide Ratio |
| DIVSLOW_A | Slow Clock Divide Ratio |
| SCS_A | System Clock Source |
Type Definitions
| DIVBUS_R | Reader of field |
| DIVCORE_R | Reader of field |
| DIVEXT_R | Reader of field |
| DIVSLOW_R | Reader of field |
| R | Reader of register CSR |
| SCS_R | Reader of field |