1#![no_std]
2#![feature(abi_riscv_interrupt)]
3
4use core::arch::global_asm;
5
6global_asm!(
7 ".attribute arch, \"rv32im\"",
9 ".section .init, \"ax\"
10 .global _start
11
12_start:
13 // zero out all registers
14 li x1, 0
15 li x2, 0
16 li x3, 0
17 li x3, 0
18 li x4, 0
19 li x6, 0
20 li x7, 0
21 li x8, 0
22 li x9, 0
23 li x10, 0
24 li x11, 0
25 li x12, 0
26 li x13, 0
27 li x14, 0
28 li x15, 0
29 li x16, 0
30 li x17, 0
31 li x18, 0
32 li x19, 0
33 li x20, 0
34 li x21, 0
35 li x22, 0
36 li x23, 0
37 li x24, 0
38 li x25, 0
39 li x26, 0
40 li x27, 0
41 li x28, 0
42 li x29, 0
43 li x30, 0
44 li x31, 0
45
46 .option push
47 .option norelax
48
49 la gp, __global_pointer$
50 .option pop
51
52 la t1, __stack_start
53 addi sp, t1, -16
54
55 la t0, _start_trap_rust
56 csrw mtvec, t0
57 // enable all interrupts
58 li t0, 0x00000003
59 csrw mie, t0
60 // enable machine-mode timer interrupt
61 li t0, 0x80
62 csrs mstatus, t0
63
64 call main
65 "
66);
67
68#[no_mangle]
69unsafe extern "riscv-interrupt-m" fn _start_trap_rust() {
70 loop {}
71}