rusty_d3d12/
const_wrappers.rs1#![allow(non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4
5use crate::raw_bindings::d3d12::*;
6use crate::utils::*;
7pub const STANDARD_MULTISAMPLE_QUALITY_PATTERN: u32 =
11 DXGI_STANDARD_MULTISAMPLE_QUALITY_PATTERN;
12pub const CENTER_MULTISAMPLE_QUALITY_PATTERN: u32 =
13 DXGI_CENTER_MULTISAMPLE_QUALITY_PATTERN;
14pub const FORMAT_DEFINED: u32 = DXGI_FORMAT_DEFINED;
15pub const C_16BIT_INDEX_STRIP_CUT_VALUE: u32 =
16 D3D12_16BIT_INDEX_STRIP_CUT_VALUE;
17pub const C_32BIT_INDEX_STRIP_CUT_VALUE: u32 =
18 D3D12_32BIT_INDEX_STRIP_CUT_VALUE;
19pub const C_8BIT_INDEX_STRIP_CUT_VALUE: u32 = D3D12_8BIT_INDEX_STRIP_CUT_VALUE;
20pub const APPEND_ALIGNED_ELEMENT: u32 = D3D12_APPEND_ALIGNED_ELEMENT;
21pub const ARRAY_AXIS_ADDRESS_RANGE_BIT_COUNT: u32 =
22 D3D12_ARRAY_AXIS_ADDRESS_RANGE_BIT_COUNT;
23pub const CLIP_OR_CULL_DISTANCE_COUNT: u32 = D3D12_CLIP_OR_CULL_DISTANCE_COUNT;
24pub const CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT: u32 =
25 D3D12_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT;
26pub const COMMONSHADER_CONSTANT_BUFFER_API_SLOT_COUNT: u32 =
27 D3D12_COMMONSHADER_CONSTANT_BUFFER_API_SLOT_COUNT;
28pub const COMMONSHADER_CONSTANT_BUFFER_COMPONENTS: u32 =
29 D3D12_COMMONSHADER_CONSTANT_BUFFER_COMPONENTS;
30pub const COMMONSHADER_CONSTANT_BUFFER_COMPONENT_BIT_COUNT: u32 =
31 D3D12_COMMONSHADER_CONSTANT_BUFFER_COMPONENT_BIT_COUNT;
32pub const COMMONSHADER_CONSTANT_BUFFER_HW_SLOT_COUNT: u32 =
33 D3D12_COMMONSHADER_CONSTANT_BUFFER_HW_SLOT_COUNT;
34pub const COMMONSHADER_CONSTANT_BUFFER_REGISTER_COMPONENTS: u32 =
35 D3D12_COMMONSHADER_CONSTANT_BUFFER_REGISTER_COMPONENTS;
36pub const COMMONSHADER_CONSTANT_BUFFER_REGISTER_COUNT: u32 =
37 D3D12_COMMONSHADER_CONSTANT_BUFFER_REGISTER_COUNT;
38pub const COMMONSHADER_CONSTANT_BUFFER_REGISTER_READS_PER_INST: u32 =
39 D3D12_COMMONSHADER_CONSTANT_BUFFER_REGISTER_READS_PER_INST;
40pub const COMMONSHADER_CONSTANT_BUFFER_REGISTER_READ_PORTS: u32 =
41 D3D12_COMMONSHADER_CONSTANT_BUFFER_REGISTER_READ_PORTS;
42pub const COMMONSHADER_FLOWCONTROL_NESTING_LIMIT: u32 =
43 D3D12_COMMONSHADER_FLOWCONTROL_NESTING_LIMIT;
44pub const COMMONSHADER_IMMEDIATE_CONSTANT_BUFFER_REGISTER_COUNT: u32 =
45 D3D12_COMMONSHADER_IMMEDIATE_CONSTANT_BUFFER_REGISTER_COUNT;
46pub const COMMONSHADER_IMMEDIATE_VALUE_COMPONENT_BIT_COUNT: u32 =
47 D3D12_COMMONSHADER_IMMEDIATE_VALUE_COMPONENT_BIT_COUNT;
48pub const COMMONSHADER_INPUT_RESOURCE_REGISTER_COMPONENTS: u32 =
49 D3D12_COMMONSHADER_INPUT_RESOURCE_REGISTER_COMPONENTS;
50pub const COMMONSHADER_INPUT_RESOURCE_REGISTER_COUNT: u32 =
51 D3D12_COMMONSHADER_INPUT_RESOURCE_REGISTER_COUNT;
52pub const COMMONSHADER_INPUT_RESOURCE_REGISTER_READS_PER_INST: u32 =
53 D3D12_COMMONSHADER_INPUT_RESOURCE_REGISTER_READS_PER_INST;
54pub const COMMONSHADER_INPUT_RESOURCE_REGISTER_READ_PORTS: u32 =
55 D3D12_COMMONSHADER_INPUT_RESOURCE_REGISTER_READ_PORTS;
56pub const COMMONSHADER_INPUT_RESOURCE_SLOT_COUNT: u32 =
57 D3D12_COMMONSHADER_INPUT_RESOURCE_SLOT_COUNT;
58pub const COMMONSHADER_SAMPLER_REGISTER_COMPONENTS: u32 =
59 D3D12_COMMONSHADER_SAMPLER_REGISTER_COMPONENTS;
60pub const COMMONSHADER_SAMPLER_REGISTER_COUNT: u32 =
61 D3D12_COMMONSHADER_SAMPLER_REGISTER_COUNT;
62pub const COMMONSHADER_SAMPLER_REGISTER_READS_PER_INST: u32 =
63 D3D12_COMMONSHADER_SAMPLER_REGISTER_READS_PER_INST;
64pub const COMMONSHADER_SAMPLER_REGISTER_READ_PORTS: u32 =
65 D3D12_COMMONSHADER_SAMPLER_REGISTER_READ_PORTS;
66pub const COMMONSHADER_SAMPLER_SLOT_COUNT: u32 =
67 D3D12_COMMONSHADER_SAMPLER_SLOT_COUNT;
68pub const COMMONSHADER_SUBROUTINE_NESTING_LIMIT: u32 =
69 D3D12_COMMONSHADER_SUBROUTINE_NESTING_LIMIT;
70pub const COMMONSHADER_TEMP_REGISTER_COMPONENTS: u32 =
71 D3D12_COMMONSHADER_TEMP_REGISTER_COMPONENTS;
72pub const COMMONSHADER_TEMP_REGISTER_COMPONENT_BIT_COUNT: u32 =
73 D3D12_COMMONSHADER_TEMP_REGISTER_COMPONENT_BIT_COUNT;
74pub const COMMONSHADER_TEMP_REGISTER_COUNT: u32 =
75 D3D12_COMMONSHADER_TEMP_REGISTER_COUNT;
76pub const COMMONSHADER_TEMP_REGISTER_READS_PER_INST: u32 =
77 D3D12_COMMONSHADER_TEMP_REGISTER_READS_PER_INST;
78pub const COMMONSHADER_TEMP_REGISTER_READ_PORTS: u32 =
79 D3D12_COMMONSHADER_TEMP_REGISTER_READ_PORTS;
80pub const COMMONSHADER_TEXCOORD_RANGE_REDUCTION_MAX: u32 =
81 D3D12_COMMONSHADER_TEXCOORD_RANGE_REDUCTION_MAX;
82pub const COMMONSHADER_TEXCOORD_RANGE_REDUCTION_MIN: i32 =
83 D3D12_COMMONSHADER_TEXCOORD_RANGE_REDUCTION_MIN;
84pub const COMMONSHADER_TEXEL_OFFSET_MAX_NEGATIVE: i32 =
85 D3D12_COMMONSHADER_TEXEL_OFFSET_MAX_NEGATIVE;
86pub const COMMONSHADER_TEXEL_OFFSET_MAX_POSITIVE: u32 =
87 D3D12_COMMONSHADER_TEXEL_OFFSET_MAX_POSITIVE;
88pub const CONSTANT_BUFFER_DATA_PLACEMENT_ALIGNMENT: ByteCount =
89 ByteCount(D3D12_CONSTANT_BUFFER_DATA_PLACEMENT_ALIGNMENT as u64);
90pub const CS_4_X_BUCKET00_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
91 D3D12_CS_4_X_BUCKET00_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
92pub const CS_4_X_BUCKET00_MAX_NUM_THREADS_PER_GROUP: u32 =
93 D3D12_CS_4_X_BUCKET00_MAX_NUM_THREADS_PER_GROUP;
94pub const CS_4_X_BUCKET01_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
95 D3D12_CS_4_X_BUCKET01_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
96pub const CS_4_X_BUCKET01_MAX_NUM_THREADS_PER_GROUP: u32 =
97 D3D12_CS_4_X_BUCKET01_MAX_NUM_THREADS_PER_GROUP;
98pub const CS_4_X_BUCKET02_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
99 D3D12_CS_4_X_BUCKET02_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
100pub const CS_4_X_BUCKET02_MAX_NUM_THREADS_PER_GROUP: u32 =
101 D3D12_CS_4_X_BUCKET02_MAX_NUM_THREADS_PER_GROUP;
102pub const CS_4_X_BUCKET03_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
103 D3D12_CS_4_X_BUCKET03_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
104pub const CS_4_X_BUCKET03_MAX_NUM_THREADS_PER_GROUP: u32 =
105 D3D12_CS_4_X_BUCKET03_MAX_NUM_THREADS_PER_GROUP;
106pub const CS_4_X_BUCKET04_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
107 D3D12_CS_4_X_BUCKET04_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
108pub const CS_4_X_BUCKET04_MAX_NUM_THREADS_PER_GROUP: u32 =
109 D3D12_CS_4_X_BUCKET04_MAX_NUM_THREADS_PER_GROUP;
110pub const CS_4_X_BUCKET05_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
111 D3D12_CS_4_X_BUCKET05_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
112pub const CS_4_X_BUCKET05_MAX_NUM_THREADS_PER_GROUP: u32 =
113 D3D12_CS_4_X_BUCKET05_MAX_NUM_THREADS_PER_GROUP;
114pub const CS_4_X_BUCKET06_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
115 D3D12_CS_4_X_BUCKET06_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
116pub const CS_4_X_BUCKET06_MAX_NUM_THREADS_PER_GROUP: u32 =
117 D3D12_CS_4_X_BUCKET06_MAX_NUM_THREADS_PER_GROUP;
118pub const CS_4_X_BUCKET07_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
119 D3D12_CS_4_X_BUCKET07_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
120pub const CS_4_X_BUCKET07_MAX_NUM_THREADS_PER_GROUP: u32 =
121 D3D12_CS_4_X_BUCKET07_MAX_NUM_THREADS_PER_GROUP;
122pub const CS_4_X_BUCKET08_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
123 D3D12_CS_4_X_BUCKET08_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
124pub const CS_4_X_BUCKET08_MAX_NUM_THREADS_PER_GROUP: u32 =
125 D3D12_CS_4_X_BUCKET08_MAX_NUM_THREADS_PER_GROUP;
126pub const CS_4_X_BUCKET09_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
127 D3D12_CS_4_X_BUCKET09_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
128pub const CS_4_X_BUCKET09_MAX_NUM_THREADS_PER_GROUP: u32 =
129 D3D12_CS_4_X_BUCKET09_MAX_NUM_THREADS_PER_GROUP;
130pub const CS_4_X_BUCKET10_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
131 D3D12_CS_4_X_BUCKET10_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
132pub const CS_4_X_BUCKET10_MAX_NUM_THREADS_PER_GROUP: u32 =
133 D3D12_CS_4_X_BUCKET10_MAX_NUM_THREADS_PER_GROUP;
134pub const CS_4_X_BUCKET11_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
135 D3D12_CS_4_X_BUCKET11_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
136pub const CS_4_X_BUCKET11_MAX_NUM_THREADS_PER_GROUP: u32 =
137 D3D12_CS_4_X_BUCKET11_MAX_NUM_THREADS_PER_GROUP;
138pub const CS_4_X_BUCKET12_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
139 D3D12_CS_4_X_BUCKET12_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
140pub const CS_4_X_BUCKET12_MAX_NUM_THREADS_PER_GROUP: u32 =
141 D3D12_CS_4_X_BUCKET12_MAX_NUM_THREADS_PER_GROUP;
142pub const CS_4_X_BUCKET13_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
143 D3D12_CS_4_X_BUCKET13_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
144pub const CS_4_X_BUCKET13_MAX_NUM_THREADS_PER_GROUP: u32 =
145 D3D12_CS_4_X_BUCKET13_MAX_NUM_THREADS_PER_GROUP;
146pub const CS_4_X_BUCKET14_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
147 D3D12_CS_4_X_BUCKET14_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
148pub const CS_4_X_BUCKET14_MAX_NUM_THREADS_PER_GROUP: u32 =
149 D3D12_CS_4_X_BUCKET14_MAX_NUM_THREADS_PER_GROUP;
150pub const CS_4_X_BUCKET15_MAX_BYTES_TGSM_WRITABLE_PER_THREAD: u32 =
151 D3D12_CS_4_X_BUCKET15_MAX_BYTES_TGSM_WRITABLE_PER_THREAD;
152pub const CS_4_X_BUCKET15_MAX_NUM_THREADS_PER_GROUP: u32 =
153 D3D12_CS_4_X_BUCKET15_MAX_NUM_THREADS_PER_GROUP;
154pub const CS_4_X_DISPATCH_MAX_THREAD_GROUPS_IN_Z_DIMENSION: u32 =
155 D3D12_CS_4_X_DISPATCH_MAX_THREAD_GROUPS_IN_Z_DIMENSION;
156pub const CS_4_X_RAW_UAV_BYTE_ALIGNMENT: ByteCount =
157 ByteCount(D3D12_CS_4_X_RAW_UAV_BYTE_ALIGNMENT as u64);
158pub const CS_4_X_THREAD_GROUP_MAX_THREADS_PER_GROUP: u32 =
159 D3D12_CS_4_X_THREAD_GROUP_MAX_THREADS_PER_GROUP;
160pub const CS_4_X_THREAD_GROUP_MAX_X: u32 = D3D12_CS_4_X_THREAD_GROUP_MAX_X;
161pub const CS_4_X_THREAD_GROUP_MAX_Y: u32 = D3D12_CS_4_X_THREAD_GROUP_MAX_Y;
162pub const CS_4_X_UAV_REGISTER_COUNT: u32 = D3D12_CS_4_X_UAV_REGISTER_COUNT;
163pub const CS_DISPATCH_MAX_THREAD_GROUPS_PER_DIMENSION: u32 =
164 D3D12_CS_DISPATCH_MAX_THREAD_GROUPS_PER_DIMENSION;
165pub const CS_TGSM_REGISTER_COUNT: u32 = D3D12_CS_TGSM_REGISTER_COUNT;
166pub const CS_TGSM_REGISTER_READS_PER_INST: u32 =
167 D3D12_CS_TGSM_REGISTER_READS_PER_INST;
168pub const CS_TGSM_RESOURCE_REGISTER_COMPONENTS: u32 =
169 D3D12_CS_TGSM_RESOURCE_REGISTER_COMPONENTS;
170pub const CS_TGSM_RESOURCE_REGISTER_READ_PORTS: u32 =
171 D3D12_CS_TGSM_RESOURCE_REGISTER_READ_PORTS;
172pub const CS_THREADGROUPID_REGISTER_COMPONENTS: u32 =
173 D3D12_CS_THREADGROUPID_REGISTER_COMPONENTS;
174pub const CS_THREADGROUPID_REGISTER_COUNT: u32 =
175 D3D12_CS_THREADGROUPID_REGISTER_COUNT;
176pub const CS_THREADIDINGROUPFLATTENED_REGISTER_COMPONENTS: u32 =
177 D3D12_CS_THREADIDINGROUPFLATTENED_REGISTER_COMPONENTS;
178pub const CS_THREADIDINGROUPFLATTENED_REGISTER_COUNT: u32 =
179 D3D12_CS_THREADIDINGROUPFLATTENED_REGISTER_COUNT;
180pub const CS_THREADIDINGROUP_REGISTER_COMPONENTS: u32 =
181 D3D12_CS_THREADIDINGROUP_REGISTER_COMPONENTS;
182pub const CS_THREADIDINGROUP_REGISTER_COUNT: u32 =
183 D3D12_CS_THREADIDINGROUP_REGISTER_COUNT;
184pub const CS_THREADID_REGISTER_COMPONENTS: u32 =
185 D3D12_CS_THREADID_REGISTER_COMPONENTS;
186pub const CS_THREADID_REGISTER_COUNT: u32 = D3D12_CS_THREADID_REGISTER_COUNT;
187pub const CS_THREAD_GROUP_MAX_THREADS_PER_GROUP: u32 =
188 D3D12_CS_THREAD_GROUP_MAX_THREADS_PER_GROUP;
189pub const CS_THREAD_GROUP_MAX_X: u32 = D3D12_CS_THREAD_GROUP_MAX_X;
190pub const CS_THREAD_GROUP_MAX_Y: u32 = D3D12_CS_THREAD_GROUP_MAX_Y;
191pub const CS_THREAD_GROUP_MAX_Z: u32 = D3D12_CS_THREAD_GROUP_MAX_Z;
192pub const CS_THREAD_GROUP_MIN_X: u32 = D3D12_CS_THREAD_GROUP_MIN_X;
193pub const CS_THREAD_GROUP_MIN_Y: u32 = D3D12_CS_THREAD_GROUP_MIN_Y;
194pub const CS_THREAD_GROUP_MIN_Z: u32 = D3D12_CS_THREAD_GROUP_MIN_Z;
195pub const CS_THREAD_LOCAL_TEMP_REGISTER_POOL: u32 =
196 D3D12_CS_THREAD_LOCAL_TEMP_REGISTER_POOL;
197pub const DEFAULT_BLEND_FACTOR_ALPHA: f64 = D3D12_DEFAULT_BLEND_FACTOR_ALPHA;
198pub const DEFAULT_BLEND_FACTOR_BLUE: f64 = D3D12_DEFAULT_BLEND_FACTOR_BLUE;
199pub const DEFAULT_BLEND_FACTOR_GREEN: f64 = D3D12_DEFAULT_BLEND_FACTOR_GREEN;
200pub const DEFAULT_BLEND_FACTOR_RED: f64 = D3D12_DEFAULT_BLEND_FACTOR_RED;
201pub const DEFAULT_BORDER_COLOR_COMPONENT: f64 =
202 D3D12_DEFAULT_BORDER_COLOR_COMPONENT;
203pub const DEFAULT_DEPTH_BIAS: u32 = D3D12_DEFAULT_DEPTH_BIAS;
204pub const DEFAULT_DEPTH_BIAS_CLAMP: f64 = D3D12_DEFAULT_DEPTH_BIAS_CLAMP;
205pub const DEFAULT_MAX_ANISOTROPY: u32 = D3D12_DEFAULT_MAX_ANISOTROPY;
206pub const DEFAULT_MIP_LOD_BIAS: f64 = D3D12_DEFAULT_MIP_LOD_BIAS;
207pub const DEFAULT_MSAA_RESOURCE_PLACEMENT_ALIGNMENT: ByteCount =
208 ByteCount(D3D12_DEFAULT_MSAA_RESOURCE_PLACEMENT_ALIGNMENT as u64);
209pub const DEFAULT_RENDER_TARGET_ARRAY_INDEX: u32 =
210 D3D12_DEFAULT_RENDER_TARGET_ARRAY_INDEX;
211pub const DEFAULT_RESOURCE_PLACEMENT_ALIGNMENT: ByteCount =
212 ByteCount(D3D12_DEFAULT_RESOURCE_PLACEMENT_ALIGNMENT as u64);
213pub const DEFAULT_SAMPLE_MASK: u32 = D3D12_DEFAULT_SAMPLE_MASK;
214pub const DEFAULT_SCISSOR_ENDX: u32 = D3D12_DEFAULT_SCISSOR_ENDX;
215pub const DEFAULT_SCISSOR_ENDY: u32 = D3D12_DEFAULT_SCISSOR_ENDY;
216pub const DEFAULT_SCISSOR_STARTX: u32 = D3D12_DEFAULT_SCISSOR_STARTX;
217pub const DEFAULT_SCISSOR_STARTY: u32 = D3D12_DEFAULT_SCISSOR_STARTY;
218pub const DEFAULT_SLOPE_SCALED_DEPTH_BIAS: f64 =
219 D3D12_DEFAULT_SLOPE_SCALED_DEPTH_BIAS;
220pub const DEFAULT_STENCIL_READ_MASK: u32 = D3D12_DEFAULT_STENCIL_READ_MASK;
221pub const DEFAULT_STENCIL_REFERENCE: u32 = D3D12_DEFAULT_STENCIL_REFERENCE;
222pub const DEFAULT_STENCIL_WRITE_MASK: u32 = D3D12_DEFAULT_STENCIL_WRITE_MASK;
223pub const DEFAULT_VIEWPORT_AND_SCISSORRECT_INDEX: u32 =
224 D3D12_DEFAULT_VIEWPORT_AND_SCISSORRECT_INDEX;
225pub const DEFAULT_VIEWPORT_HEIGHT: u32 = D3D12_DEFAULT_VIEWPORT_HEIGHT;
226pub const DEFAULT_VIEWPORT_MAX_DEPTH: f64 = D3D12_DEFAULT_VIEWPORT_MAX_DEPTH;
227pub const DEFAULT_VIEWPORT_MIN_DEPTH: f64 = D3D12_DEFAULT_VIEWPORT_MIN_DEPTH;
228pub const DEFAULT_VIEWPORT_TOPLEFTX: u32 = D3D12_DEFAULT_VIEWPORT_TOPLEFTX;
229pub const DEFAULT_VIEWPORT_TOPLEFTY: u32 = D3D12_DEFAULT_VIEWPORT_TOPLEFTY;
230pub const DEFAULT_VIEWPORT_WIDTH: u32 = D3D12_DEFAULT_VIEWPORT_WIDTH;
231pub const DESCRIPTOR_RANGE_OFFSET_APPEND: u32 =
232 D3D12_DESCRIPTOR_RANGE_OFFSET_APPEND;
233pub const DRIVER_RESERVED_REGISTER_SPACE_VALUES_END: u32 =
234 D3D12_DRIVER_RESERVED_REGISTER_SPACE_VALUES_END;
235pub const DRIVER_RESERVED_REGISTER_SPACE_VALUES_START: u32 =
236 D3D12_DRIVER_RESERVED_REGISTER_SPACE_VALUES_START;
237pub const DS_INPUT_CONTROL_POINTS_MAX_TOTAL_SCALARS: u32 =
238 D3D12_DS_INPUT_CONTROL_POINTS_MAX_TOTAL_SCALARS;
239pub const DS_INPUT_CONTROL_POINT_REGISTER_COMPONENTS: u32 =
240 D3D12_DS_INPUT_CONTROL_POINT_REGISTER_COMPONENTS;
241pub const DS_INPUT_CONTROL_POINT_REGISTER_COMPONENT_BIT_COUNT: u32 =
242 D3D12_DS_INPUT_CONTROL_POINT_REGISTER_COMPONENT_BIT_COUNT;
243pub const DS_INPUT_CONTROL_POINT_REGISTER_COUNT: u32 =
244 D3D12_DS_INPUT_CONTROL_POINT_REGISTER_COUNT;
245pub const DS_INPUT_CONTROL_POINT_REGISTER_READS_PER_INST: u32 =
246 D3D12_DS_INPUT_CONTROL_POINT_REGISTER_READS_PER_INST;
247pub const DS_INPUT_CONTROL_POINT_REGISTER_READ_PORTS: u32 =
248 D3D12_DS_INPUT_CONTROL_POINT_REGISTER_READ_PORTS;
249pub const DS_INPUT_DOMAIN_POINT_REGISTER_COMPONENTS: u32 =
250 D3D12_DS_INPUT_DOMAIN_POINT_REGISTER_COMPONENTS;
251pub const DS_INPUT_DOMAIN_POINT_REGISTER_COMPONENT_BIT_COUNT: u32 =
252 D3D12_DS_INPUT_DOMAIN_POINT_REGISTER_COMPONENT_BIT_COUNT;
253pub const DS_INPUT_DOMAIN_POINT_REGISTER_COUNT: u32 =
254 D3D12_DS_INPUT_DOMAIN_POINT_REGISTER_COUNT;
255pub const DS_INPUT_DOMAIN_POINT_REGISTER_READS_PER_INST: u32 =
256 D3D12_DS_INPUT_DOMAIN_POINT_REGISTER_READS_PER_INST;
257pub const DS_INPUT_DOMAIN_POINT_REGISTER_READ_PORTS: u32 =
258 D3D12_DS_INPUT_DOMAIN_POINT_REGISTER_READ_PORTS;
259pub const DS_INPUT_PATCH_CONSTANT_REGISTER_COMPONENTS: u32 =
260 D3D12_DS_INPUT_PATCH_CONSTANT_REGISTER_COMPONENTS;
261pub const DS_INPUT_PATCH_CONSTANT_REGISTER_COMPONENT_BIT_COUNT: u32 =
262 D3D12_DS_INPUT_PATCH_CONSTANT_REGISTER_COMPONENT_BIT_COUNT;
263pub const DS_INPUT_PATCH_CONSTANT_REGISTER_COUNT: u32 =
264 D3D12_DS_INPUT_PATCH_CONSTANT_REGISTER_COUNT;
265pub const DS_INPUT_PATCH_CONSTANT_REGISTER_READS_PER_INST: u32 =
266 D3D12_DS_INPUT_PATCH_CONSTANT_REGISTER_READS_PER_INST;
267pub const DS_INPUT_PATCH_CONSTANT_REGISTER_READ_PORTS: u32 =
268 D3D12_DS_INPUT_PATCH_CONSTANT_REGISTER_READ_PORTS;
269pub const DS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENTS: u32 =
270 D3D12_DS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENTS;
271pub const DS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENT_BIT_COUNT: u32 =
272 D3D12_DS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENT_BIT_COUNT;
273pub const DS_INPUT_PRIMITIVE_ID_REGISTER_COUNT: u32 =
274 D3D12_DS_INPUT_PRIMITIVE_ID_REGISTER_COUNT;
275pub const DS_INPUT_PRIMITIVE_ID_REGISTER_READS_PER_INST: u32 =
276 D3D12_DS_INPUT_PRIMITIVE_ID_REGISTER_READS_PER_INST;
277pub const DS_INPUT_PRIMITIVE_ID_REGISTER_READ_PORTS: u32 =
278 D3D12_DS_INPUT_PRIMITIVE_ID_REGISTER_READ_PORTS;
279pub const DS_OUTPUT_REGISTER_COMPONENTS: u32 =
280 D3D12_DS_OUTPUT_REGISTER_COMPONENTS;
281pub const DS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT: u32 =
282 D3D12_DS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT;
283pub const DS_OUTPUT_REGISTER_COUNT: u32 = D3D12_DS_OUTPUT_REGISTER_COUNT;
284pub const FLOAT16_FUSED_TOLERANCE_IN_ULP: f64 =
285 D3D12_FLOAT16_FUSED_TOLERANCE_IN_ULP;
286pub const FLOAT32_TO_INTEGER_TOLERANCE_IN_ULP: f64 =
287 D3D12_FLOAT32_TO_INTEGER_TOLERANCE_IN_ULP;
288pub const FLOAT_TO_SRGB_EXPONENT_DENOMINATOR: f64 =
289 D3D12_FLOAT_TO_SRGB_EXPONENT_DENOMINATOR;
290pub const FLOAT_TO_SRGB_EXPONENT_NUMERATOR: f64 =
291 D3D12_FLOAT_TO_SRGB_EXPONENT_NUMERATOR;
292pub const FLOAT_TO_SRGB_OFFSET: f64 = D3D12_FLOAT_TO_SRGB_OFFSET;
293pub const FLOAT_TO_SRGB_SCALE_1: f64 = D3D12_FLOAT_TO_SRGB_SCALE_1;
294pub const FLOAT_TO_SRGB_SCALE_2: f64 = D3D12_FLOAT_TO_SRGB_SCALE_2;
295pub const FLOAT_TO_SRGB_THRESHOLD: f64 = D3D12_FLOAT_TO_SRGB_THRESHOLD;
296pub const FTOI_INSTRUCTION_MAX_INPUT: f64 = D3D12_FTOI_INSTRUCTION_MAX_INPUT;
297pub const FTOI_INSTRUCTION_MIN_INPUT: f64 = D3D12_FTOI_INSTRUCTION_MIN_INPUT;
298pub const FTOU_INSTRUCTION_MAX_INPUT: f64 = D3D12_FTOU_INSTRUCTION_MAX_INPUT;
299pub const FTOU_INSTRUCTION_MIN_INPUT: f64 = D3D12_FTOU_INSTRUCTION_MIN_INPUT;
300pub const GS_INPUT_INSTANCE_ID_READS_PER_INST: u32 =
301 D3D12_GS_INPUT_INSTANCE_ID_READS_PER_INST;
302pub const GS_INPUT_INSTANCE_ID_READ_PORTS: u32 =
303 D3D12_GS_INPUT_INSTANCE_ID_READ_PORTS;
304pub const GS_INPUT_INSTANCE_ID_REGISTER_COMPONENTS: u32 =
305 D3D12_GS_INPUT_INSTANCE_ID_REGISTER_COMPONENTS;
306pub const GS_INPUT_INSTANCE_ID_REGISTER_COMPONENT_BIT_COUNT: u32 =
307 D3D12_GS_INPUT_INSTANCE_ID_REGISTER_COMPONENT_BIT_COUNT;
308pub const GS_INPUT_INSTANCE_ID_REGISTER_COUNT: u32 =
309 D3D12_GS_INPUT_INSTANCE_ID_REGISTER_COUNT;
310pub const GS_INPUT_PRIM_CONST_REGISTER_COMPONENTS: u32 =
311 D3D12_GS_INPUT_PRIM_CONST_REGISTER_COMPONENTS;
312pub const GS_INPUT_PRIM_CONST_REGISTER_COMPONENT_BIT_COUNT: u32 =
313 D3D12_GS_INPUT_PRIM_CONST_REGISTER_COMPONENT_BIT_COUNT;
314pub const GS_INPUT_PRIM_CONST_REGISTER_COUNT: u32 =
315 D3D12_GS_INPUT_PRIM_CONST_REGISTER_COUNT;
316pub const GS_INPUT_PRIM_CONST_REGISTER_READS_PER_INST: u32 =
317 D3D12_GS_INPUT_PRIM_CONST_REGISTER_READS_PER_INST;
318pub const GS_INPUT_PRIM_CONST_REGISTER_READ_PORTS: u32 =
319 D3D12_GS_INPUT_PRIM_CONST_REGISTER_READ_PORTS;
320pub const GS_INPUT_REGISTER_COMPONENTS: u32 =
321 D3D12_GS_INPUT_REGISTER_COMPONENTS;
322pub const GS_INPUT_REGISTER_COMPONENT_BIT_COUNT: u32 =
323 D3D12_GS_INPUT_REGISTER_COMPONENT_BIT_COUNT;
324pub const GS_INPUT_REGISTER_COUNT: u32 = D3D12_GS_INPUT_REGISTER_COUNT;
325pub const GS_INPUT_REGISTER_READS_PER_INST: u32 =
326 D3D12_GS_INPUT_REGISTER_READS_PER_INST;
327pub const GS_INPUT_REGISTER_READ_PORTS: u32 =
328 D3D12_GS_INPUT_REGISTER_READ_PORTS;
329pub const GS_INPUT_REGISTER_VERTICES: u32 = D3D12_GS_INPUT_REGISTER_VERTICES;
330pub const GS_MAX_INSTANCE_COUNT: u32 = D3D12_GS_MAX_INSTANCE_COUNT;
331pub const GS_MAX_OUTPUT_VERTEX_COUNT_ACROSS_INSTANCES: u32 =
332 D3D12_GS_MAX_OUTPUT_VERTEX_COUNT_ACROSS_INSTANCES;
333pub const GS_OUTPUT_ELEMENTS: u32 = D3D12_GS_OUTPUT_ELEMENTS;
334pub const GS_OUTPUT_REGISTER_COMPONENTS: u32 =
335 D3D12_GS_OUTPUT_REGISTER_COMPONENTS;
336pub const GS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT: u32 =
337 D3D12_GS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT;
338pub const GS_OUTPUT_REGISTER_COUNT: u32 = D3D12_GS_OUTPUT_REGISTER_COUNT;
339pub const HS_CONTROL_POINT_PHASE_INPUT_REGISTER_COUNT: u32 =
340 D3D12_HS_CONTROL_POINT_PHASE_INPUT_REGISTER_COUNT;
341pub const HS_CONTROL_POINT_PHASE_OUTPUT_REGISTER_COUNT: u32 =
342 D3D12_HS_CONTROL_POINT_PHASE_OUTPUT_REGISTER_COUNT;
343pub const HS_CONTROL_POINT_REGISTER_COMPONENTS: u32 =
344 D3D12_HS_CONTROL_POINT_REGISTER_COMPONENTS;
345pub const HS_CONTROL_POINT_REGISTER_COMPONENT_BIT_COUNT: u32 =
346 D3D12_HS_CONTROL_POINT_REGISTER_COMPONENT_BIT_COUNT;
347pub const HS_CONTROL_POINT_REGISTER_READS_PER_INST: u32 =
348 D3D12_HS_CONTROL_POINT_REGISTER_READS_PER_INST;
349pub const HS_CONTROL_POINT_REGISTER_READ_PORTS: u32 =
350 D3D12_HS_CONTROL_POINT_REGISTER_READ_PORTS;
351pub const HS_FORK_PHASE_INSTANCE_COUNT_UPPER_BOUND: u32 =
352 D3D12_HS_FORK_PHASE_INSTANCE_COUNT_UPPER_BOUND;
353pub const HS_INPUT_FORK_INSTANCE_ID_REGISTER_COMPONENTS: u32 =
354 D3D12_HS_INPUT_FORK_INSTANCE_ID_REGISTER_COMPONENTS;
355pub const HS_INPUT_FORK_INSTANCE_ID_REGISTER_COUNT: u32 =
356 D3D12_HS_INPUT_FORK_INSTANCE_ID_REGISTER_COUNT;
357pub const HS_INPUT_FORK_INSTANCE_ID_REGISTER_READS_PER_INST: u32 =
358 D3D12_HS_INPUT_FORK_INSTANCE_ID_REGISTER_READS_PER_INST;
359pub const HS_INPUT_FORK_INSTANCE_ID_REGISTER_READ_PORTS: u32 =
360 D3D12_HS_INPUT_FORK_INSTANCE_ID_REGISTER_READ_PORTS;
361pub const HS_INPUT_JOIN_INSTANCE_ID_REGISTER_COMPONENTS: u32 =
362 D3D12_HS_INPUT_JOIN_INSTANCE_ID_REGISTER_COMPONENTS;
363pub const HS_INPUT_JOIN_INSTANCE_ID_REGISTER_COUNT: u32 =
364 D3D12_HS_INPUT_JOIN_INSTANCE_ID_REGISTER_COUNT;
365pub const HS_INPUT_JOIN_INSTANCE_ID_REGISTER_READS_PER_INST: u32 =
366 D3D12_HS_INPUT_JOIN_INSTANCE_ID_REGISTER_READS_PER_INST;
367pub const HS_INPUT_JOIN_INSTANCE_ID_REGISTER_READ_PORTS: u32 =
368 D3D12_HS_INPUT_JOIN_INSTANCE_ID_REGISTER_READ_PORTS;
369pub const HS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENTS: u32 =
370 D3D12_HS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENTS;
371pub const HS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENT_BIT_COUNT: u32 =
372 D3D12_HS_INPUT_PRIMITIVE_ID_REGISTER_COMPONENT_BIT_COUNT;
373pub const HS_INPUT_PRIMITIVE_ID_REGISTER_COUNT: u32 =
374 D3D12_HS_INPUT_PRIMITIVE_ID_REGISTER_COUNT;
375pub const HS_INPUT_PRIMITIVE_ID_REGISTER_READS_PER_INST: u32 =
376 D3D12_HS_INPUT_PRIMITIVE_ID_REGISTER_READS_PER_INST;
377pub const HS_INPUT_PRIMITIVE_ID_REGISTER_READ_PORTS: u32 =
378 D3D12_HS_INPUT_PRIMITIVE_ID_REGISTER_READ_PORTS;
379pub const HS_JOIN_PHASE_INSTANCE_COUNT_UPPER_BOUND: u32 =
380 D3D12_HS_JOIN_PHASE_INSTANCE_COUNT_UPPER_BOUND;
381pub const HS_MAXTESSFACTOR_LOWER_BOUND: f64 =
382 D3D12_HS_MAXTESSFACTOR_LOWER_BOUND;
383pub const HS_MAXTESSFACTOR_UPPER_BOUND: f64 =
384 D3D12_HS_MAXTESSFACTOR_UPPER_BOUND;
385pub const HS_OUTPUT_CONTROL_POINTS_MAX_TOTAL_SCALARS: u32 =
386 D3D12_HS_OUTPUT_CONTROL_POINTS_MAX_TOTAL_SCALARS;
387pub const HS_OUTPUT_CONTROL_POINT_ID_REGISTER_COMPONENTS: u32 =
388 D3D12_HS_OUTPUT_CONTROL_POINT_ID_REGISTER_COMPONENTS;
389pub const HS_OUTPUT_CONTROL_POINT_ID_REGISTER_COUNT: u32 =
390 D3D12_HS_OUTPUT_CONTROL_POINT_ID_REGISTER_COUNT;
391pub const HS_OUTPUT_CONTROL_POINT_ID_REGISTER_READS_PER_INST: u32 =
392 D3D12_HS_OUTPUT_CONTROL_POINT_ID_REGISTER_READS_PER_INST;
393pub const HS_OUTPUT_CONTROL_POINT_ID_REGISTER_READ_PORTS: u32 =
394 D3D12_HS_OUTPUT_CONTROL_POINT_ID_REGISTER_READ_PORTS;
395pub const HS_OUTPUT_PATCH_CONSTANT_REGISTER_COMPONENTS: u32 =
396 D3D12_HS_OUTPUT_PATCH_CONSTANT_REGISTER_COMPONENTS;
397pub const HS_OUTPUT_PATCH_CONSTANT_REGISTER_COMPONENT_BIT_COUNT: u32 =
398 D3D12_HS_OUTPUT_PATCH_CONSTANT_REGISTER_COMPONENT_BIT_COUNT;
399pub const HS_OUTPUT_PATCH_CONSTANT_REGISTER_COUNT: u32 =
400 D3D12_HS_OUTPUT_PATCH_CONSTANT_REGISTER_COUNT;
401pub const HS_OUTPUT_PATCH_CONSTANT_REGISTER_READS_PER_INST: u32 =
402 D3D12_HS_OUTPUT_PATCH_CONSTANT_REGISTER_READS_PER_INST;
403pub const HS_OUTPUT_PATCH_CONSTANT_REGISTER_READ_PORTS: u32 =
404 D3D12_HS_OUTPUT_PATCH_CONSTANT_REGISTER_READ_PORTS;
405pub const HS_OUTPUT_PATCH_CONSTANT_REGISTER_SCALAR_COMPONENTS: u32 =
406 D3D12_HS_OUTPUT_PATCH_CONSTANT_REGISTER_SCALAR_COMPONENTS;
407pub const IA_DEFAULT_INDEX_BUFFER_OFFSET: ByteCount =
408 ByteCount(D3D12_IA_DEFAULT_INDEX_BUFFER_OFFSET_IN_BYTES as u64);
409pub const IA_DEFAULT_PRIMITIVE_TOPOLOGY: u32 =
410 D3D12_IA_DEFAULT_PRIMITIVE_TOPOLOGY;
411pub const IA_DEFAULT_VERTEX_BUFFER_OFFSET: ByteCount =
412 ByteCount(D3D12_IA_DEFAULT_VERTEX_BUFFER_OFFSET_IN_BYTES as u64);
413pub const IA_INDEX_INPUT_RESOURCE_SLOT_COUNT: u32 =
414 D3D12_IA_INDEX_INPUT_RESOURCE_SLOT_COUNT;
415pub const IA_INSTANCE_ID_BIT_COUNT: u32 = D3D12_IA_INSTANCE_ID_BIT_COUNT;
416pub const IA_INTEGER_ARITHMETIC_BIT_COUNT: u32 =
417 D3D12_IA_INTEGER_ARITHMETIC_BIT_COUNT;
418pub const IA_PATCH_MAX_CONTROL_POINT_COUNT: u32 =
419 D3D12_IA_PATCH_MAX_CONTROL_POINT_COUNT;
420pub const IA_PRIMITIVE_ID_BIT_COUNT: u32 = D3D12_IA_PRIMITIVE_ID_BIT_COUNT;
421pub const IA_VERTEX_ID_BIT_COUNT: u32 = D3D12_IA_VERTEX_ID_BIT_COUNT;
422pub const IA_VERTEX_INPUT_RESOURCE_SLOT_COUNT: u32 =
423 D3D12_IA_VERTEX_INPUT_RESOURCE_SLOT_COUNT;
424pub const IA_VERTEX_INPUT_STRUCTURE_ELEMENTS_COMPONENTS: u32 =
425 D3D12_IA_VERTEX_INPUT_STRUCTURE_ELEMENTS_COMPONENTS;
426pub const IA_VERTEX_INPUT_STRUCTURE_ELEMENT_COUNT: u32 =
427 D3D12_IA_VERTEX_INPUT_STRUCTURE_ELEMENT_COUNT;
428pub const INTEGER_DIVIDE_BY_ZERO_QUOTIENT: u32 =
429 D3D12_INTEGER_DIVIDE_BY_ZERO_QUOTIENT;
430pub const INTEGER_DIVIDE_BY_ZERO_REMAINDER: u32 =
431 D3D12_INTEGER_DIVIDE_BY_ZERO_REMAINDER;
432pub const KEEP_RENDER_TARGETS_AND_DEPTH_STENCIL: u32 =
433 D3D12_KEEP_RENDER_TARGETS_AND_DEPTH_STENCIL;
434pub const KEEP_UNORDERED_ACCESS_VIEWS: u32 = D3D12_KEEP_UNORDERED_ACCESS_VIEWS;
435pub const LINEAR_GAMMA: f64 = D3D12_LINEAR_GAMMA;
436pub const MAJOR_VERSION: u32 = D3D12_MAJOR_VERSION;
437pub const MAX_BORDER_COLOR_COMPONENT: f64 = D3D12_MAX_BORDER_COLOR_COMPONENT;
438pub const MAX_DEPTH: f64 = D3D12_MAX_DEPTH;
439pub const MAX_LIVE_STATIC_SAMPLERS: u32 = D3D12_MAX_LIVE_STATIC_SAMPLERS;
440pub const MAX_MAXANISOTROPY: u32 = D3D12_MAX_MAXANISOTROPY;
441pub const MAX_MULTISAMPLE_SAMPLE_COUNT: u32 =
442 D3D12_MAX_MULTISAMPLE_SAMPLE_COUNT;
443pub const MAX_ROOT_COST: u32 = D3D12_MAX_ROOT_COST;
444pub const MAX_SHADER_VISIBLE_DESCRIPTOR_HEAP_SIZE_TIER_1: u32 =
445 D3D12_MAX_SHADER_VISIBLE_DESCRIPTOR_HEAP_SIZE_TIER_1;
446pub const MAX_SHADER_VISIBLE_DESCRIPTOR_HEAP_SIZE_TIER_2: u32 =
447 D3D12_MAX_SHADER_VISIBLE_DESCRIPTOR_HEAP_SIZE_TIER_2;
448pub const MAX_SHADER_VISIBLE_SAMPLER_HEAP_SIZE: u32 =
449 D3D12_MAX_SHADER_VISIBLE_SAMPLER_HEAP_SIZE;
450pub const MAX_TEXTURE_DIMENSION_2_TO_EXP: u32 =
451 D3D12_MAX_TEXTURE_DIMENSION_2_TO_EXP;
452pub const MAX_VIEW_INSTANCE_COUNT: u32 = D3D12_MAX_VIEW_INSTANCE_COUNT;
453pub const MINOR_VERSION: u32 = D3D12_MINOR_VERSION;
454pub const MIN_BORDER_COLOR_COMPONENT: f64 = D3D12_MIN_BORDER_COLOR_COMPONENT;
455pub const MIN_DEPTH: f64 = D3D12_MIN_DEPTH;
456pub const MIN_MAXANISOTROPY: u32 = D3D12_MIN_MAXANISOTROPY;
457pub const MIP_LOD_BIAS_MAX: f64 = D3D12_MIP_LOD_BIAS_MAX;
458pub const MIP_LOD_BIAS_MIN: f64 = D3D12_MIP_LOD_BIAS_MIN;
459pub const MIP_LOD_FRACTIONAL_BIT_COUNT: u32 =
460 D3D12_MIP_LOD_FRACTIONAL_BIT_COUNT;
461pub const MIP_LOD_RANGE_BIT_COUNT: u32 = D3D12_MIP_LOD_RANGE_BIT_COUNT;
462pub const MULTISAMPLE_ANTIALIAS_LINE_WIDTH: f64 =
463 D3D12_MULTISAMPLE_ANTIALIAS_LINE_WIDTH;
464pub const NONSAMPLE_FETCH_OUT_OF_RANGE_ACCESS_RESULT: u32 =
465 D3D12_NONSAMPLE_FETCH_OUT_OF_RANGE_ACCESS_RESULT;
466pub const OS_RESERVED_REGISTER_SPACE_VALUES_END: u32 =
467 D3D12_OS_RESERVED_REGISTER_SPACE_VALUES_END;
468pub const OS_RESERVED_REGISTER_SPACE_VALUES_START: u32 =
469 D3D12_OS_RESERVED_REGISTER_SPACE_VALUES_START;
470pub const PACKED_TILE: u32 = D3D12_PACKED_TILE;
471pub const PIXEL_ADDRESS_RANGE_BIT_COUNT: u32 =
472 D3D12_PIXEL_ADDRESS_RANGE_BIT_COUNT;
473pub const PRE_SCISSOR_PIXEL_ADDRESS_RANGE_BIT_COUNT: u32 =
474 D3D12_PRE_SCISSOR_PIXEL_ADDRESS_RANGE_BIT_COUNT;
475pub const PS_CS_UAV_REGISTER_COMPONENTS: u32 =
476 D3D12_PS_CS_UAV_REGISTER_COMPONENTS;
477pub const PS_CS_UAV_REGISTER_COUNT: u32 = D3D12_PS_CS_UAV_REGISTER_COUNT;
478pub const PS_CS_UAV_REGISTER_READS_PER_INST: u32 =
479 D3D12_PS_CS_UAV_REGISTER_READS_PER_INST;
480pub const PS_CS_UAV_REGISTER_READ_PORTS: u32 =
481 D3D12_PS_CS_UAV_REGISTER_READ_PORTS;
482pub const PS_FRONTFACING_DEFAULT_VALUE: u32 =
483 D3D12_PS_FRONTFACING_DEFAULT_VALUE;
484pub const PS_FRONTFACING_FALSE_VALUE: u32 = D3D12_PS_FRONTFACING_FALSE_VALUE;
485pub const PS_FRONTFACING_TRUE_VALUE: u32 = D3D12_PS_FRONTFACING_TRUE_VALUE;
486pub const PS_INPUT_REGISTER_COMPONENTS: u32 =
487 D3D12_PS_INPUT_REGISTER_COMPONENTS;
488pub const PS_INPUT_REGISTER_COMPONENT_BIT_COUNT: u32 =
489 D3D12_PS_INPUT_REGISTER_COMPONENT_BIT_COUNT;
490pub const PS_INPUT_REGISTER_COUNT: u32 = D3D12_PS_INPUT_REGISTER_COUNT;
491pub const PS_INPUT_REGISTER_READS_PER_INST: u32 =
492 D3D12_PS_INPUT_REGISTER_READS_PER_INST;
493pub const PS_INPUT_REGISTER_READ_PORTS: u32 =
494 D3D12_PS_INPUT_REGISTER_READ_PORTS;
495pub const PS_LEGACY_PIXEL_CENTER_FRACTIONAL_COMPONENT: f64 =
496 D3D12_PS_LEGACY_PIXEL_CENTER_FRACTIONAL_COMPONENT;
497pub const PS_OUTPUT_DEPTH_REGISTER_COMPONENTS: u32 =
498 D3D12_PS_OUTPUT_DEPTH_REGISTER_COMPONENTS;
499pub const PS_OUTPUT_DEPTH_REGISTER_COMPONENT_BIT_COUNT: u32 =
500 D3D12_PS_OUTPUT_DEPTH_REGISTER_COMPONENT_BIT_COUNT;
501pub const PS_OUTPUT_DEPTH_REGISTER_COUNT: u32 =
502 D3D12_PS_OUTPUT_DEPTH_REGISTER_COUNT;
503pub const PS_OUTPUT_MASK_REGISTER_COMPONENTS: u32 =
504 D3D12_PS_OUTPUT_MASK_REGISTER_COMPONENTS;
505pub const PS_OUTPUT_MASK_REGISTER_COMPONENT_BIT_COUNT: u32 =
506 D3D12_PS_OUTPUT_MASK_REGISTER_COMPONENT_BIT_COUNT;
507pub const PS_OUTPUT_MASK_REGISTER_COUNT: u32 =
508 D3D12_PS_OUTPUT_MASK_REGISTER_COUNT;
509pub const PS_OUTPUT_REGISTER_COMPONENTS: u32 =
510 D3D12_PS_OUTPUT_REGISTER_COMPONENTS;
511pub const PS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT: u32 =
512 D3D12_PS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT;
513pub const PS_OUTPUT_REGISTER_COUNT: u32 = D3D12_PS_OUTPUT_REGISTER_COUNT;
514pub const PS_PIXEL_CENTER_FRACTIONAL_COMPONENT: f64 =
515 D3D12_PS_PIXEL_CENTER_FRACTIONAL_COMPONENT;
516pub const RAW_UAV_SRV_BYTE_ALIGNMENT: ByteCount =
517 ByteCount(D3D12_RAW_UAV_SRV_BYTE_ALIGNMENT as u64);
518pub const RAYTRACING_AABB_BYTE_ALIGNMENT: ByteCount =
519 ByteCount(D3D12_RAYTRACING_AABB_BYTE_ALIGNMENT as u64);
520pub const RAYTRACING_ACCELERATION_STRUCTURE_BYTE_ALIGNMENT: ByteCount =
521 ByteCount(D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BYTE_ALIGNMENT as u64);
522pub const RAYTRACING_INSTANCE_DESCS_BYTE_ALIGNMENT: ByteCount =
523 ByteCount(D3D12_RAYTRACING_INSTANCE_DESCS_BYTE_ALIGNMENT as u64);
524pub const RAYTRACING_MAX_ATTRIBUTE_SIZE: ByteCount =
525 ByteCount(D3D12_RAYTRACING_MAX_ATTRIBUTE_SIZE_IN_BYTES as u64);
526pub const RAYTRACING_MAX_DECLARABLE_TRACE_RECURSION_DEPTH: u32 =
527 D3D12_RAYTRACING_MAX_DECLARABLE_TRACE_RECURSION_DEPTH;
528pub const RAYTRACING_MAX_RAY_GENERATION_SHADER_THREADS: u32 =
529 D3D12_RAYTRACING_MAX_RAY_GENERATION_SHADER_THREADS;
530pub const RAYTRACING_MAX_SHADER_RECORD_STRIDE: u32 =
531 D3D12_RAYTRACING_MAX_SHADER_RECORD_STRIDE;
532pub const RAYTRACING_SHADER_RECORD_BYTE_ALIGNMENT: ByteCount =
533 ByteCount(D3D12_RAYTRACING_SHADER_RECORD_BYTE_ALIGNMENT as u64);
534pub const RAYTRACING_SHADER_TABLE_BYTE_ALIGNMENT: ByteCount =
535 ByteCount(D3D12_RAYTRACING_SHADER_TABLE_BYTE_ALIGNMENT as u64);
536pub const RAYTRACING_TRANSFORM3X4_BYTE_ALIGNMENT: ByteCount =
537 ByteCount(D3D12_RAYTRACING_TRANSFORM3X4_BYTE_ALIGNMENT as u64);
538pub const REQ_BLEND_OBJECT_COUNT_PER_DEVICE: u32 =
539 D3D12_REQ_BLEND_OBJECT_COUNT_PER_DEVICE;
540pub const REQ_BUFFER_RESOURCE_TEXEL_COUNT_2_TO_EXP: u32 =
541 D3D12_REQ_BUFFER_RESOURCE_TEXEL_COUNT_2_TO_EXP;
542pub const REQ_CONSTANT_BUFFER_ELEMENT_COUNT: u32 =
543 D3D12_REQ_CONSTANT_BUFFER_ELEMENT_COUNT;
544pub const REQ_DEPTH_STENCIL_OBJECT_COUNT_PER_DEVICE: u32 =
545 D3D12_REQ_DEPTH_STENCIL_OBJECT_COUNT_PER_DEVICE;
546pub const REQ_DRAWINDEXED_INDEX_COUNT_2_TO_EXP: u32 =
547 D3D12_REQ_DRAWINDEXED_INDEX_COUNT_2_TO_EXP;
548pub const REQ_DRAW_VERTEX_COUNT_2_TO_EXP: u32 =
549 D3D12_REQ_DRAW_VERTEX_COUNT_2_TO_EXP;
550pub const REQ_FILTERING_HW_ADDRESSABLE_RESOURCE_DIMENSION: u32 =
551 D3D12_REQ_FILTERING_HW_ADDRESSABLE_RESOURCE_DIMENSION;
552pub const REQ_GS_INVOCATION_32BIT_OUTPUT_COMPONENT_LIMIT: u32 =
553 D3D12_REQ_GS_INVOCATION_32BIT_OUTPUT_COMPONENT_LIMIT;
554pub const REQ_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT: u32 =
555 D3D12_REQ_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT;
556pub const REQ_MAXANISOTROPY: u32 = D3D12_REQ_MAXANISOTROPY;
557pub const REQ_MIP_LEVELS: u32 = D3D12_REQ_MIP_LEVELS;
558pub const REQ_MULTI_ELEMENT_STRUCTURE_SIZE: ByteCount =
559 ByteCount(D3D12_REQ_MULTI_ELEMENT_STRUCTURE_SIZE_IN_BYTES as u64);
560pub const REQ_RASTERIZER_OBJECT_COUNT_PER_DEVICE: u32 =
561 D3D12_REQ_RASTERIZER_OBJECT_COUNT_PER_DEVICE;
562pub const REQ_RENDER_TO_BUFFER_WINDOW_WIDTH: u32 =
563 D3D12_REQ_RENDER_TO_BUFFER_WINDOW_WIDTH;
564pub const REQ_RESOURCE_SIZE_IN_MEGABYTES_EXPRESSION_A_TERM: u32 =
565 D3D12_REQ_RESOURCE_SIZE_IN_MEGABYTES_EXPRESSION_A_TERM;
566pub const REQ_RESOURCE_SIZE_IN_MEGABYTES_EXPRESSION_B_TERM: f64 =
567 D3D12_REQ_RESOURCE_SIZE_IN_MEGABYTES_EXPRESSION_B_TERM;
568pub const REQ_RESOURCE_SIZE_IN_MEGABYTES_EXPRESSION_C_TERM: u32 =
569 D3D12_REQ_RESOURCE_SIZE_IN_MEGABYTES_EXPRESSION_C_TERM;
570pub const REQ_RESOURCE_VIEW_COUNT_PER_DEVICE_2_TO_EXP: u32 =
571 D3D12_REQ_RESOURCE_VIEW_COUNT_PER_DEVICE_2_TO_EXP;
572pub const REQ_SAMPLER_OBJECT_COUNT_PER_DEVICE: u32 =
573 D3D12_REQ_SAMPLER_OBJECT_COUNT_PER_DEVICE;
574pub const REQ_SUBRESOURCES: u32 = D3D12_REQ_SUBRESOURCES;
575pub const REQ_TEXTURE1D_ARRAY_AXIS_DIMENSION: u32 =
576 D3D12_REQ_TEXTURE1D_ARRAY_AXIS_DIMENSION;
577pub const REQ_TEXTURE1D_U_DIMENSION: u32 = D3D12_REQ_TEXTURE1D_U_DIMENSION;
578pub const REQ_TEXTURE2D_ARRAY_AXIS_DIMENSION: u32 =
579 D3D12_REQ_TEXTURE2D_ARRAY_AXIS_DIMENSION;
580pub const REQ_TEXTURE2D_U_OR_V_DIMENSION: u32 =
581 D3D12_REQ_TEXTURE2D_U_OR_V_DIMENSION;
582pub const REQ_TEXTURE3D_U_V_OR_W_DIMENSION: u32 =
583 D3D12_REQ_TEXTURE3D_U_V_OR_W_DIMENSION;
584pub const REQ_TEXTURECUBE_DIMENSION: u32 = D3D12_REQ_TEXTURECUBE_DIMENSION;
585pub const RESINFO_INSTRUCTION_MISSING_COMPONENT_RETVAL: u32 =
586 D3D12_RESINFO_INSTRUCTION_MISSING_COMPONENT_RETVAL;
587pub const RESOURCE_BARRIER_ALL_SUBRESOURCES: u32 =
588 D3D12_RESOURCE_BARRIER_ALL_SUBRESOURCES;
589pub const RS_SET_SHADING_RATE_COMBINER_COUNT: u32 =
590 D3D12_RS_SET_SHADING_RATE_COMBINER_COUNT;
591pub const SDK_VERSION: u32 = D3D12_SDK_VERSION;
592pub const SHADER_IDENTIFIER_SIZE: ByteCount =
593 ByteCount(D3D12_SHADER_IDENTIFIER_SIZE_IN_BYTES as u64);
594pub const SHADER_MAJOR_VERSION: u32 = D3D12_SHADER_MAJOR_VERSION;
595pub const SHADER_MAX_INSTANCES: u32 = D3D12_SHADER_MAX_INSTANCES;
596pub const SHADER_MAX_INTERFACES: u32 = D3D12_SHADER_MAX_INTERFACES;
597pub const SHADER_MAX_INTERFACE_CALL_SITES: u32 =
598 D3D12_SHADER_MAX_INTERFACE_CALL_SITES;
599pub const SHADER_MAX_TYPES: u32 = D3D12_SHADER_MAX_TYPES;
600pub const SHADER_MINOR_VERSION: u32 = D3D12_SHADER_MINOR_VERSION;
601pub const SHIFT_INSTRUCTION_PAD_VALUE: u32 = D3D12_SHIFT_INSTRUCTION_PAD_VALUE;
602pub const SHIFT_INSTRUCTION_SHIFT_VALUE_BIT_COUNT: u32 =
603 D3D12_SHIFT_INSTRUCTION_SHIFT_VALUE_BIT_COUNT;
604pub const SIMULTANEOUS_RENDER_TARGET_COUNT: u32 =
605 D3D12_SIMULTANEOUS_RENDER_TARGET_COUNT;
606pub const SMALL_MSAA_RESOURCE_PLACEMENT_ALIGNMENT: ByteCount =
607 ByteCount(D3D12_SMALL_MSAA_RESOURCE_PLACEMENT_ALIGNMENT as u64);
608pub const SMALL_RESOURCE_PLACEMENT_ALIGNMENT: ByteCount =
609 ByteCount(D3D12_SMALL_RESOURCE_PLACEMENT_ALIGNMENT as u64);
610pub const SO_BUFFER_MAX_STRIDE: ByteCount =
611 ByteCount(D3D12_SO_BUFFER_MAX_STRIDE_IN_BYTES as u64);
612pub const SO_BUFFER_MAX_WRITE_WINDOW: ByteCount =
613 ByteCount(D3D12_SO_BUFFER_MAX_WRITE_WINDOW_IN_BYTES as u64);
614pub const SO_BUFFER_SLOT_COUNT: u32 = D3D12_SO_BUFFER_SLOT_COUNT;
615pub const SO_DDI_REGISTER_INDEX_DENOTING_GAP: u32 =
616 D3D12_SO_DDI_REGISTER_INDEX_DENOTING_GAP;
617pub const SO_NO_RASTERIZED_STREAM: u32 = D3D12_SO_NO_RASTERIZED_STREAM;
618pub const SO_OUTPUT_COMPONENT_COUNT: u32 = D3D12_SO_OUTPUT_COMPONENT_COUNT;
619pub const SO_STREAM_COUNT: u32 = D3D12_SO_STREAM_COUNT;
620pub const SPEC_DATE_DAY: u32 = D3D12_SPEC_DATE_DAY;
621pub const SPEC_DATE_MONTH: u32 = D3D12_SPEC_DATE_MONTH;
622pub const SPEC_DATE_YEAR: u32 = D3D12_SPEC_DATE_YEAR;
623pub const SPEC_VERSION: f64 = D3D12_SPEC_VERSION;
624pub const SRGB_GAMMA: f64 = D3D12_SRGB_GAMMA;
625pub const SRGB_TO_FLOAT_DENOMINATOR_1: f64 = D3D12_SRGB_TO_FLOAT_DENOMINATOR_1;
626pub const SRGB_TO_FLOAT_DENOMINATOR_2: f64 = D3D12_SRGB_TO_FLOAT_DENOMINATOR_2;
627pub const SRGB_TO_FLOAT_EXPONENT: f64 = D3D12_SRGB_TO_FLOAT_EXPONENT;
628pub const SRGB_TO_FLOAT_OFFSET: f64 = D3D12_SRGB_TO_FLOAT_OFFSET;
629pub const SRGB_TO_FLOAT_THRESHOLD: f64 = D3D12_SRGB_TO_FLOAT_THRESHOLD;
630pub const SRGB_TO_FLOAT_TOLERANCE_IN_ULP: f64 =
631 D3D12_SRGB_TO_FLOAT_TOLERANCE_IN_ULP;
632pub const STANDARD_COMPONENT_BIT_COUNT: u32 =
633 D3D12_STANDARD_COMPONENT_BIT_COUNT;
634pub const STANDARD_COMPONENT_BIT_COUNT_DOUBLED: u32 =
635 D3D12_STANDARD_COMPONENT_BIT_COUNT_DOUBLED;
636pub const STANDARD_MAXIMUM_ELEMENT_ALIGNMENT_BYTE_MULTIPLE: u32 =
637 D3D12_STANDARD_MAXIMUM_ELEMENT_ALIGNMENT_BYTE_MULTIPLE;
638pub const STANDARD_PIXEL_COMPONENT_COUNT: u32 =
639 D3D12_STANDARD_PIXEL_COMPONENT_COUNT;
640pub const STANDARD_PIXEL_ELEMENT_COUNT: u32 =
641 D3D12_STANDARD_PIXEL_ELEMENT_COUNT;
642pub const STANDARD_VECTOR_SIZE: u32 = D3D12_STANDARD_VECTOR_SIZE;
643pub const STANDARD_VERTEX_ELEMENT_COUNT: u32 =
644 D3D12_STANDARD_VERTEX_ELEMENT_COUNT;
645pub const STANDARD_VERTEX_TOTAL_COMPONENT_COUNT: u32 =
646 D3D12_STANDARD_VERTEX_TOTAL_COMPONENT_COUNT;
647pub const SUBPIXEL_FRACTIONAL_BIT_COUNT: u32 =
648 D3D12_SUBPIXEL_FRACTIONAL_BIT_COUNT;
649pub const SUBTEXEL_FRACTIONAL_BIT_COUNT: u32 =
650 D3D12_SUBTEXEL_FRACTIONAL_BIT_COUNT;
651pub const SYSTEM_RESERVED_REGISTER_SPACE_VALUES_END: u32 =
652 D3D12_SYSTEM_RESERVED_REGISTER_SPACE_VALUES_END;
653pub const SYSTEM_RESERVED_REGISTER_SPACE_VALUES_START: u32 =
654 D3D12_SYSTEM_RESERVED_REGISTER_SPACE_VALUES_START;
655pub const TESSELLATOR_MAX_EVEN_TESSELLATION_FACTOR: u32 =
656 D3D12_TESSELLATOR_MAX_EVEN_TESSELLATION_FACTOR;
657pub const TESSELLATOR_MAX_ISOLINE_DENSITY_TESSELLATION_FACTOR: u32 =
658 D3D12_TESSELLATOR_MAX_ISOLINE_DENSITY_TESSELLATION_FACTOR;
659pub const TESSELLATOR_MAX_ODD_TESSELLATION_FACTOR: u32 =
660 D3D12_TESSELLATOR_MAX_ODD_TESSELLATION_FACTOR;
661pub const TESSELLATOR_MAX_TESSELLATION_FACTOR: u32 =
662 D3D12_TESSELLATOR_MAX_TESSELLATION_FACTOR;
663pub const TESSELLATOR_MIN_EVEN_TESSELLATION_FACTOR: u32 =
664 D3D12_TESSELLATOR_MIN_EVEN_TESSELLATION_FACTOR;
665pub const TESSELLATOR_MIN_ISOLINE_DENSITY_TESSELLATION_FACTOR: u32 =
666 D3D12_TESSELLATOR_MIN_ISOLINE_DENSITY_TESSELLATION_FACTOR;
667pub const TESSELLATOR_MIN_ODD_TESSELLATION_FACTOR: u32 =
668 D3D12_TESSELLATOR_MIN_ODD_TESSELLATION_FACTOR;
669pub const TEXEL_ADDRESS_RANGE_BIT_COUNT: u32 =
670 D3D12_TEXEL_ADDRESS_RANGE_BIT_COUNT;
671pub const TEXTURE_DATA_PITCH_ALIGNMENT: ByteCount =
672 ByteCount(D3D12_TEXTURE_DATA_PITCH_ALIGNMENT as u64);
673pub const TEXTURE_DATA_PLACEMENT_ALIGNMENT: ByteCount =
674 ByteCount(D3D12_TEXTURE_DATA_PLACEMENT_ALIGNMENT as u64);
675pub const TILED_RESOURCE_TILE_SIZE: ByteCount =
676 ByteCount(D3D12_TILED_RESOURCE_TILE_SIZE_IN_BYTES as u64);
677pub const TRACKED_WORKLOAD_MAX_INSTANCES: u32 =
678 D3D12_TRACKED_WORKLOAD_MAX_INSTANCES;
679pub const UAV_COUNTER_PLACEMENT_ALIGNMENT: ByteCount =
680 ByteCount(D3D12_UAV_COUNTER_PLACEMENT_ALIGNMENT as u64);
681pub const UAV_SLOT_COUNT: u32 = D3D12_UAV_SLOT_COUNT;
682pub const UNBOUND_MEMORY_ACCESS_RESULT: u32 =
683 D3D12_UNBOUND_MEMORY_ACCESS_RESULT;
684pub const VIDEO_DECODE_MAX_ARGUMENTS: u32 = D3D12_VIDEO_DECODE_MAX_ARGUMENTS;
685pub const VIDEO_DECODE_MAX_HISTOGRAM_COMPONENTS: u32 =
686 D3D12_VIDEO_DECODE_MAX_HISTOGRAM_COMPONENTS;
687pub const VIDEO_DECODE_MIN_BITSTREAM_OFFSET_ALIGNMENT: ByteCount =
688 ByteCount(D3D12_VIDEO_DECODE_MIN_BITSTREAM_OFFSET_ALIGNMENT as u64);
689pub const VIDEO_DECODE_MIN_HISTOGRAM_OFFSET_ALIGNMENT: ByteCount =
690 ByteCount(D3D12_VIDEO_DECODE_MIN_HISTOGRAM_OFFSET_ALIGNMENT as u64);
691pub const VIDEO_PROCESS_MAX_FILTERS: u32 = D3D12_VIDEO_PROCESS_MAX_FILTERS;
692pub const VIDEO_PROCESS_STEREO_VIEWS: u32 = D3D12_VIDEO_PROCESS_STEREO_VIEWS;
693pub const VIEWPORT_AND_SCISSORRECT_MAX_INDEX: u32 =
694 D3D12_VIEWPORT_AND_SCISSORRECT_MAX_INDEX;
695pub const VIEWPORT_AND_SCISSORRECT_OBJECT_COUNT_PER_PIPELINE: u32 =
696 D3D12_VIEWPORT_AND_SCISSORRECT_OBJECT_COUNT_PER_PIPELINE;
697pub const VIEWPORT_BOUNDS_MAX: u32 = D3D12_VIEWPORT_BOUNDS_MAX;
698pub const VIEWPORT_BOUNDS_MIN: i32 = D3D12_VIEWPORT_BOUNDS_MIN;
699pub const VS_INPUT_REGISTER_COMPONENTS: u32 =
700 D3D12_VS_INPUT_REGISTER_COMPONENTS;
701pub const VS_INPUT_REGISTER_COMPONENT_BIT_COUNT: u32 =
702 D3D12_VS_INPUT_REGISTER_COMPONENT_BIT_COUNT;
703pub const VS_INPUT_REGISTER_COUNT: u32 = D3D12_VS_INPUT_REGISTER_COUNT;
704pub const VS_INPUT_REGISTER_READS_PER_INST: u32 =
705 D3D12_VS_INPUT_REGISTER_READS_PER_INST;
706pub const VS_INPUT_REGISTER_READ_PORTS: u32 =
707 D3D12_VS_INPUT_REGISTER_READ_PORTS;
708pub const VS_OUTPUT_REGISTER_COMPONENTS: u32 =
709 D3D12_VS_OUTPUT_REGISTER_COMPONENTS;
710pub const VS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT: u32 =
711 D3D12_VS_OUTPUT_REGISTER_COMPONENT_BIT_COUNT;
712pub const VS_OUTPUT_REGISTER_COUNT: u32 = D3D12_VS_OUTPUT_REGISTER_COUNT;
713pub const WHQL_CONTEXT_COUNT_FOR_RESOURCE_LIMIT: u32 =
714 D3D12_WHQL_CONTEXT_COUNT_FOR_RESOURCE_LIMIT;
715pub const WHQL_DRAWINDEXED_INDEX_COUNT_2_TO_EXP: u32 =
716 D3D12_WHQL_DRAWINDEXED_INDEX_COUNT_2_TO_EXP;
717pub const WHQL_DRAW_VERTEX_COUNT_2_TO_EXP: u32 =
718 D3D12_WHQL_DRAW_VERTEX_COUNT_2_TO_EXP;
719pub const SHADER_COMPONENT_MAPPING_MASK: u32 =
720 D3D12_SHADER_COMPONENT_MAPPING_MASK;
721pub const SHADER_COMPONENT_MAPPING_SHIFT: u32 =
722 D3D12_SHADER_COMPONENT_MAPPING_SHIFT;
723pub const FILTER_REDUCTION_TYPE_MASK: u32 = D3D12_FILTER_REDUCTION_TYPE_MASK;
724pub const FILTER_REDUCTION_TYPE_SHIFT: u32 = D3D12_FILTER_REDUCTION_TYPE_SHIFT;
725pub const FILTER_TYPE_MASK: u32 = D3D12_FILTER_TYPE_MASK;
726pub const MIN_FILTER_SHIFT: u32 = D3D12_MIN_FILTER_SHIFT;
727pub const MAG_FILTER_SHIFT: u32 = D3D12_MAG_FILTER_SHIFT;
728pub const MIP_FILTER_SHIFT: u32 = D3D12_MIP_FILTER_SHIFT;
729pub const ANISOTROPIC_FILTERING_BIT: u32 = D3D12_ANISOTROPIC_FILTERING_BIT;
730pub const INFO_QUEUE_DEFAULT_MESSAGE_COUNT_LIMIT: u32 =
731 D3D12_INFO_QUEUE_DEFAULT_MESSAGE_COUNT_LIMIT;
732pub const SHADING_RATE_X_AXIS_SHIFT: u32 = D3D12_SHADING_RATE_X_AXIS_SHIFT;
733pub const SHADING_RATE_VALID_MASK: u32 = D3D12_SHADING_RATE_VALID_MASK;
734pub const CPU_ACCESS_NONE: u32 = DXGI_CPU_ACCESS_NONE;
735pub const CPU_ACCESS_DYNAMIC: u32 = DXGI_CPU_ACCESS_DYNAMIC;
736pub const CPU_ACCESS_READ_WRITE: u32 = DXGI_CPU_ACCESS_READ_WRITE;
737pub const CPU_ACCESS_SCRATCH: u32 = DXGI_CPU_ACCESS_SCRATCH;
738pub const CPU_ACCESS_FIELD: u32 = DXGI_CPU_ACCESS_FIELD;
739pub const USAGE_SHADER_INPUT: u32 = DXGI_USAGE_SHADER_INPUT;
740pub const USAGE_RENDER_TARGET_OUTPUT: u32 = DXGI_USAGE_RENDER_TARGET_OUTPUT;
741pub const USAGE_BACK_BUFFER: u32 = DXGI_USAGE_BACK_BUFFER;
742pub const USAGE_SHARED: u32 = DXGI_USAGE_SHARED;
743pub const USAGE_READ_ONLY: u32 = DXGI_USAGE_READ_ONLY;
744pub const USAGE_DISCARD_ON_PRESENT: u32 = DXGI_USAGE_DISCARD_ON_PRESENT;
745pub const USAGE_UNORDERED_ACCESS: u32 = DXGI_USAGE_UNORDERED_ACCESS;
746pub const RESOURCE_PRIORITY_MINIMUM: u32 = DXGI_RESOURCE_PRIORITY_MINIMUM;
747pub const RESOURCE_PRIORITY_LOW: u32 = DXGI_RESOURCE_PRIORITY_LOW;
748pub const RESOURCE_PRIORITY_NORMAL: u32 = DXGI_RESOURCE_PRIORITY_NORMAL;
749pub const RESOURCE_PRIORITY_HIGH: u32 = DXGI_RESOURCE_PRIORITY_HIGH;
750pub const RESOURCE_PRIORITY_MAXIMUM: u32 = DXGI_RESOURCE_PRIORITY_MAXIMUM;
751pub const MAP_READ: u32 = DXGI_MAP_READ;
752pub const MAP_WRITE: u32 = DXGI_MAP_WRITE;
753pub const MAP_DISCARD: u32 = DXGI_MAP_DISCARD;
754pub const ENUM_MODES_INTERLACED: u32 = DXGI_ENUM_MODES_INTERLACED;
755pub const ENUM_MODES_SCALING: u32 = DXGI_ENUM_MODES_SCALING;
756pub const MAX_SWAP_CHAIN_BUFFERS: u32 = DXGI_MAX_SWAP_CHAIN_BUFFERS;
757pub const PRESENT_TEST: u32 = DXGI_PRESENT_TEST;
758pub const PRESENT_DO_NOT_SEQUENCE: u32 = DXGI_PRESENT_DO_NOT_SEQUENCE;
759pub const PRESENT_RESTART: u32 = DXGI_PRESENT_RESTART;
760pub const PRESENT_DO_NOT_WAIT: u32 = DXGI_PRESENT_DO_NOT_WAIT;
761pub const PRESENT_STEREO_PREFER_RIGHT: u32 = DXGI_PRESENT_STEREO_PREFER_RIGHT;
762pub const PRESENT_STEREO_TEMPORARY_MONO: u32 =
763 DXGI_PRESENT_STEREO_TEMPORARY_MONO;
764pub const PRESENT_RESTRICT_TO_OUTPUT: u32 = DXGI_PRESENT_RESTRICT_TO_OUTPUT;
765pub const PRESENT_USE_DURATION: u32 = DXGI_PRESENT_USE_DURATION;
766pub const PRESENT_ALLOW_TEARING: u32 = DXGI_PRESENT_ALLOW_TEARING;
767pub const MWA_NO_WINDOW_CHANGES: u32 = DXGI_MWA_NO_WINDOW_CHANGES;
768pub const MWA_NO_ALT_ENTER: u32 = DXGI_MWA_NO_ALT_ENTER;
769pub const MWA_NO_PRINT_SCREEN: u32 = DXGI_MWA_NO_PRINT_SCREEN;
770pub const MWA_VALID: u32 = DXGI_MWA_VALID;
771pub const ENUM_MODES_STEREO: u32 = DXGI_ENUM_MODES_STEREO;
772pub const ENUM_MODES_DISABLED_STEREO: u32 = DXGI_ENUM_MODES_DISABLED_STEREO;
773pub const SHARED_RESOURCE_READ: u32 = DXGI_SHARED_RESOURCE_READ;
774pub const SHARED_RESOURCE_WRITE: u32 = DXGI_SHARED_RESOURCE_WRITE;
775pub const CREATE_FACTORY_DEBUG: u32 = DXGI_CREATE_FACTORY_DEBUG;