rustsbi_jh7110/
lib.rs

1//! RustSBI-JH7110 is an implementation of the [RustSBI](https://github.com/rustsbi/rustsbi) traits, and the [SBI](https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc) extensions relevant for the JH7110 SoC.
2//!
3//! The project includes a library to create your own SBI firmware, and a standalone binary
4//! reference implementation.
5
6#![no_std]
7
8#[cfg(target_arch = "riscv64")]
9pub mod asm;
10pub mod bits;
11#[cfg(target_arch = "riscv64")]
12pub mod clint;
13#[cfg(target_arch = "riscv64")]
14pub mod console;
15#[cfg(target_arch = "riscv64")]
16pub mod early_trap;
17pub mod ecall;
18pub mod env_info;
19mod error;
20#[cfg(target_arch = "riscv64")]
21pub mod exception;
22#[cfg(target_arch = "riscv64")]
23pub mod executor;
24pub mod fw_dynamic_info;
25pub mod harts;
26#[cfg(target_arch = "riscv64")]
27pub mod hpm;
28#[cfg(target_arch = "riscv64")]
29pub mod init;
30#[cfg(target_arch = "riscv64")]
31pub mod ipi;
32#[cfg(target_arch = "riscv64")]
33pub mod kernel;
34pub mod l2pm;
35mod macros;
36#[cfg(target_arch = "riscv64")]
37pub mod pmp;
38#[cfg(target_arch = "riscv64")]
39pub mod pmu;
40pub mod probe;
41#[cfg(target_arch = "riscv64")]
42pub mod register;
43#[cfg(target_arch = "riscv64")]
44pub mod rfence;
45#[cfg(target_arch = "riscv64")]
46pub mod sbi;
47#[cfg(target_arch = "riscv64")]
48pub mod scratch;
49#[cfg(target_arch = "riscv64")]
50pub mod timer;
51pub mod tlb;
52#[cfg(target_arch = "riscv64")]
53pub mod trap;
54#[cfg(target_arch = "riscv64")]
55mod util;
56pub mod version;
57
58pub use error::*;
59#[cfg(target_arch = "riscv64")]
60pub(crate) use util::*;
61
62#[cfg(target_arch = "riscv64")]
63pub use sbi::*;
64
65/// 16 KiB stack for each HART
66pub const PER_HART_STACK_SIZE: usize = 16384;
67/// 5 HARTS
68pub const SBI_STACK_SIZE: usize = 5 * PER_HART_STACK_SIZE;
69
70#[link_section = ".bss.uninit"]
71pub static mut SBI_STACK: [u8; SBI_STACK_SIZE] = [0; SBI_STACK_SIZE];