Module phase 

Phase triggers (ReadOnly / ReadWrite / NextTimeStep) and the scheduled write buffer (design-doc §4.1(4), §4.4, mapping rows 15 & 22).

One hub per sim thread coordinates: writes via set() are buffered and drained at the start of the next ReadWrite phase — before ReadWrite awaiters are woken — porting cocotb’s write scheduler verbatim (cocotb: handle.py _apply_scheduled_writes, ReadWrite._do_callbacks). Illegal phase transitions (write/await-ReadWrite from ReadOnly) are runtime errors, exactly as cocotb.

Structs

PhaseFut

Enums

SimPhase

Functions

current_phase

leave_read_only

Return to a region where writing is legal.

next_time_step

Await the next simulator time step (port of NextTimeStep()).

read_only

Await the next ReadOnly phase (port of ReadOnly()).

read_write

Await the next ReadWrite phase (port of ReadWrite()).