rustdv_methodology/
rustdv_methodology.rs

1//! # rustdv-methodology
2//!
3//! The verification methodology layer — rustdv's analog of the UVM's
4//! component methodology (design-doc §5, as revised by review-memo R1–R6).
5//!
6//! **Read this first: R3, R4 and R5 are being reversed.** They are what
7//! made rustdv a *closed-world* framework — one that cannot configure or
8//! override anything you did not write yourself — and the branch this
9//! crate is on exists to undo them. `output/.design-decisions.md` is
10//! authoritative; the list below marks each item's real status so nobody
11//! mistakes the current code for the intended design.
12//!
13//! - Transactions are plain structs with std derives (R1) — no base trait.
14//!   **Stands.**
15//! - The component tree is the ownership tree (R2): children are struct
16//!   fields; [`ComponentNode`] provides traversal, hand-implementable or
17//!   generated by `#[derive(Component)]`. **Stands** — the tree is still
18//!   ownership; what returns is the phase structure over it.
19//! - build/connect are constructor conventions (R3); the runtime lifecycle
20//!   is the [`Component`] trait. **Reversed — `build`/`connect` are real
21//!   phase methods again (D5/D6/D51), and the runner drives all nine phases
22//!   over the tree (`run_component_test`).** The *first half* of ch24 (the
23//!   phase-logging test) runs on this. Still pending: two-stage
24//!   construction, where a parent creates children as `Option<T>`/`Vec<T>`
25//!   in its own `build` — the second half of ch24.
26//! - Configuration is typed config structs passed to constructors (R4).
27//!   **Reversed by D11–D16, not yet implemented.** A path-addressed
28//!   `ConfigDb` returns, with three-tier resolution and loud failure.
29//! - Variation points are constructor injection (R5) — no factory.
30//!   **Reversed, not yet implemented.** The factory returns in ch29
31//!   (D26 keeps it out of ch23 only because the book does).
32//! - Communication is channels + [`AnalysisBus`] + the sequencer
33//!   handshake, preserved event-for-event from pyuvm (R6, §5.6).
34//!   **Stands, and is being extended:** TLM ports, exports and FIFOs
35//!   arrive per D17–D24, with ports in components and exports on FIFOs.
36//!
37//! What *has* landed on this branch is step 4: [`RustdvCtx`], the one
38//! context (D47), and [`Component`]'s `async fn run` (D46, D48).
39
40pub mod analysis;
41pub mod channel;
42#[cfg(test)]
43use rustdv_vpi_stubs as _;
44
45pub mod component;
46pub mod config;
47pub mod error;
48pub mod factory;
49pub mod fifo;
50pub mod objection;
51pub mod port;
52pub mod sequence;
53pub mod shared;
54
55pub use analysis::{AnalysisBus, PublishExport, SubscribeExport};
56pub use channel::{Receiver, Sender, TlmEmpty, TlmError, TlmFull, channel};
57pub use component::{
58    Active, CheckSink, Component, ComponentNode, DynPhases, RustdvCtx, build_all, check_all,
59    check_connections, connect_all, end_of_elaboration_all, extract_all, final_all,
60    print_hierarchy, report_all, run_all, run_component_test, run_extract_check_report, start_all,
61    start_of_simulation_all, unconnected_ports,
62};
63pub use config::{ConfigDb, ConfigError};
64pub use error::TestError;
65pub use factory::{COMPONENT_REGISTRATIONS, ComponentReg, Factory, Maker, RustdvComp};
66pub use fifo::{GetExport, PeekExport, PutExport, TapExport, TlmFifo};
67pub use objection::{ObjectionGuard, ObjectionRegistry};
68pub use port::{
69    ConnectError, GetIf, GetPort, PeekIf, PeekPort, Port, PortField, PortInfo, PortName, PortOwner,
70    PublishIf, PublishPort, PutIf, PutPort, SinkHandle, SubscribePort, Subscriber, bind,
71};
72pub use sequence::{
73    DynSequence, ResponseQueue, RustdvSeq, SeqCtx, SeqError, SeqItem, SeqItemExport, SeqItemIf,
74    SeqItemPort, Sequence, Sequencer, TxnId, clear_seq_overrides, create_seq, set_seq_override,
75    set_sequence_seed,
76};
77pub use shared::RustdvShared;
rustdv_methodology/rustdv_methodology.rs

rustdv_methodology/
rustdv_methodology.rs
