rust_hdl_lib_widgets/
registered_edge_tristate.rs

1use rust_hdl_lib_core::prelude::*;
2
3use crate::{dff::DFF, dff_setup};
4
5#[derive(LogicBlock, Default)]
6pub struct RegisteredEdgeTristate<const W: usize> {
7    pub bus: Signal<InOut, Bits<W>>,
8    pub write_enable: Signal<In, Bit>,
9    pub write_data: Signal<In, Bits<W>>,
10    pub read_data: Signal<Out, Bits<W>>,
11    pub clock: Signal<In, Clock>,
12    dff_out: DFF<Bits<W>>,
13    dff_in: DFF<Bits<W>>,
14}
15
16impl<const W: usize> Logic for RegisteredEdgeTristate<W> {
17    fn update(&mut self) {
18        dff_setup!(self, clock, dff_out, dff_in);
19        if self.write_enable.val() {
20            self.bus.next = self.dff_out.q.val();
21        }
22        self.dff_in.d.next = self.bus.val();
23        self.read_data.next = self.dff_in.q.val();
24        self.bus.set_tristate_is_output(self.write_enable.val());
25        self.dff_out.d.next = self.write_data.val();
26    }
27    fn connect(&mut self) {
28        self.dff_out.clock.connect();
29        self.dff_in.clock.connect();
30        self.dff_in.d.connect();
31        self.dff_out.d.connect();
32        self.bus.connect();
33        self.read_data.connect();
34    }
35    fn hdl(&self) -> Verilog {
36        Verilog::Wrapper(Wrapper {
37            code: format!(
38                r#"
39
40reg [{WIDTH}:0] dff_in;
41reg [{WIDTH}:0] dff_out;
42assign bus = write_enable ? dff_out : {WIDTH}'bz;
43assign read_data = dff_in;
44always @(posedge clock) begin
45      dff_in <= bus;
46end
47always @(posedge clock) begin
48      dff_out <= write_data;
49end
50            "#,
51                WIDTH = W - 1
52            ),
53            cores: r#""#.to_string(),
54        })
55    }
56}
57
58#[test]
59fn test_tristate_edge_synthesizes() {
60    let mut uut = RegisteredEdgeTristate::<8>::default();
61    uut.connect_all();
62    let vlog = generate_verilog(&uut);
63    yosys_validate("tristate_reg", &vlog).unwrap()
64}
rust_hdl_lib_widgets/registered_edge_tristate.rs

rust_hdl_lib_widgets/
registered_edge_tristate.rs
