rust_hdl_lib_hls/
bus.rs

1// A simple, local bus for attaching stuff together on the FPGA
2use rust_hdl_lib_core::prelude::*;
3
4// Ultimately, a device will have multiple ports.  It will represent
5// a "chunk" of bus addresses that can be communicated with via the
6// controller.  The question is how do those addresses get routed
7// and what do they mean.  Suppose we have 5 ports to describe a
8// device.  The natural way to integrate those is to stack them
9// behind a bridge:
10//
11//              +-------
12//  --- bus --> | port 1
13//              | port 2
14//              |   |
15//              | port 5
16//              +-------
17//
18// This means each port simply needs a "chip-select" type line, and the address
19// of the port is N + base, where base is the base address of the bridge.
20//
21// We can then stack bridges using a router.  The router will need to assign
22// non-overlapping addresses to the bridges, and route the traffic based
23// on those ranges.  For example, if there are 2 of these 5-port devices
24// attached to bridges B1 and B2.  Then we need to do something like
25//
26//             +--------+              +-------
27//             |        | ---- bus --> |  B1
28//  -- bus --> |        |              +-------
29//             |        | ---- bus --> |  B2
30//             +--------+              +-------
31
32#[derive(Clone, Debug, Default, LogicInterface)]
33#[join = "SoCBusResponder"]
34pub struct SoCBusController<const D: usize, const A: usize> {
35    pub address: Signal<Out, Bits<A>>,
36    pub address_strobe: Signal<Out, Bit>,
37    pub from_controller: Signal<Out, Bits<D>>,
38    pub to_controller: Signal<In, Bits<D>>,
39    pub ready: Signal<In, Bit>,
40    pub strobe: Signal<Out, Bit>,
41    pub clock: Signal<Out, Clock>,
42}
43
44#[derive(Clone, Debug, Default, LogicInterface)]
45#[join = "SoCBusController"]
46pub struct SoCBusResponder<const D: usize, const A: usize> {
47    pub address: Signal<In, Bits<A>>,
48    pub address_strobe: Signal<In, Bit>,
49    pub from_controller: Signal<In, Bits<D>>,
50    pub to_controller: Signal<Out, Bits<D>>,
51    pub ready: Signal<Out, Bit>,
52    pub strobe: Signal<In, Bit>,
53    pub clock: Signal<In, Clock>,
54}
55
56#[derive(Clone, Debug, Default, LogicInterface)]
57#[join = "SoCPortResponder"]
58pub struct SoCPortController<const D: usize> {
59    pub select: Signal<Out, Bit>,
60    pub from_controller: Signal<Out, Bits<D>>,
61    pub to_controller: Signal<In, Bits<D>>,
62    pub ready: Signal<In, Bit>,
63    pub strobe: Signal<Out, Bit>,
64    pub clock: Signal<Out, Clock>,
65}
66
67#[derive(Clone, Debug, Default, LogicInterface)]
68#[join = "SoCPortController"]
69pub struct SoCPortResponder<const D: usize> {
70    pub select: Signal<In, Bit>,
71    pub from_controller: Signal<In, Bits<D>>,
72    pub to_controller: Signal<Out, Bits<D>>,
73    pub ready: Signal<Out, Bit>,
74    pub strobe: Signal<In, Bit>,
75    pub clock: Signal<In, Clock>,
76}
77
78#[derive(Clone, Debug, Default, LogicInterface)]
79#[join = "FIFOWriteResponder"]
80pub struct FIFOWriteController<T: Synth> {
81    pub data: Signal<Out, T>,
82    pub write: Signal<Out, Bit>,
83    pub full: Signal<In, Bit>,
84    pub almost_full: Signal<In, Bit>,
85}
86
87#[derive(Clone, Debug, Default, LogicInterface)]
88#[join = "FIFOWriteController"]
89pub struct FIFOWriteResponder<T: Synth> {
90    pub data: Signal<In, T>,
91    pub write: Signal<In, Bit>,
92    pub full: Signal<Out, Bit>,
93    pub almost_full: Signal<Out, Bit>,
94}
95
96#[derive(Clone, Debug, Default, LogicInterface)]
97#[join = "FIFOReadResponder"]
98pub struct FIFOReadController<T: Synth> {
99    pub data: Signal<In, T>,
100    pub read: Signal<Out, Bit>,
101    pub empty: Signal<In, Bit>,
102    pub almost_empty: Signal<In, Bit>,
103}
104
105#[derive(Clone, Debug, Default, LogicInterface)]
106#[join = "FIFOReadController"]
107pub struct FIFOReadResponder<T: Synth> {
108    pub data: Signal<Out, T>,
109    pub read: Signal<In, Bit>,
110    pub empty: Signal<Out, Bit>,
111    pub almost_empty: Signal<Out, Bit>,
112}
rust_hdl_lib_hls/bus.rs

rust_hdl_lib_hls/
bus.rs
