rust_hdl_lib_hls/
sim.rs

1#[macro_export]
2macro_rules! hls_fifo_write_lazy {
3    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo:ident).+, $data: expr) => {
4        wait_clock_true!($sim, $($clock).+, $uut);
5        for val in $data {
6            // Wait for the FIFO to not be full
7            $uut = $sim.watch(|x| !x.$($fifo).+.full.val(), $uut)?;
8            // Set the data lines and pulse the write signal
9            $uut.$($fifo).+.data.next = (*val).to_bits();
10            $uut.$($fifo).+.write.next = true;
11            wait_clock_cycle!($sim, $($clock).+, $uut);
12            $uut.$($fifo).+.write.next = false;
13            if rand::thread_rng().gen::<f64>() < 0.2 {
14                for _ in 0..(rand::thread_rng().gen::<u8>() % 40) {
15                    wait_clock_cycle!($sim, $($clock).+, $uut);
16                }
17            }
18        }
19    }
20}
21
22#[macro_export]
23macro_rules! hls_fifo_write {
24    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo:ident).+, $data: expr) => {
25        wait_clock_true!($sim, $($clock).+, $uut);
26        for val in $data {
27            // Wait for the FIFO to not be full
28            $uut = $sim.watch(|x| !x.$($fifo).+.full.val(), $uut)?;
29            // Set the data lines and pulse the write signal
30            $uut.$($fifo).+.data.next = val.to_bits();
31            $uut.$($fifo).+.write.next = true;
32            wait_clock_cycle!($sim, $($clock).+, $uut);
33            $uut.$($fifo).+.write.next = false;
34        }
35    }
36}
37
38#[macro_export]
39macro_rules! hls_fifo_read {
40    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo:ident).*, $data: expr) => {
41        wait_clock_true!($sim, $($clock).+, $uut);
42        for val in $data {
43            $uut = $sim.watch(|x| !x.$($fifo).+.empty.val(), $uut)?;
44            sim_assert_eq!($sim, $uut.$($fifo).+.data.val(), (*val) as LiteralType, $uut);
45            $uut.$($fifo).+.read.next = true;
46            wait_clock_cycle!($sim, $($clock).+, $uut);
47            $uut.$($fifo).+.read.next = false;
48        }
49    }
50}
51
52#[macro_export]
53macro_rules! hls_fifo_read_lazy {
54    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo:ident).*, $data: expr) => {
55        wait_clock_true!($sim, $($clock).+, $uut);
56        for val in $data {
57            $uut = $sim.watch(|x| !x.$($fifo).+.empty.val(), $uut)?;
58            sim_assert_eq!($sim, $uut.$($fifo).+.data.val(), (*val) as LiteralType, $uut);
59            $uut.$($fifo).+.read.next = true;
60            wait_clock_cycle!($sim, $($clock).+, $uut);
61            $uut.$($fifo).+.read.next = false;
62            if rand::thread_rng().gen::<f64>() < 0.2 {
63                for _ in 0..(rand::thread_rng().gen::<u8>() % 40) {
64                    wait_clock_cycle!($sim, $($clock).+, $uut);
65                }
66            }
67        }
68    }
69}
70
71#[macro_export]
72macro_rules! hls_host_get_word {
73    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo:ident).*) => {
74        {
75        wait_clock_true!($sim, $($clock).+, $uut);
76        let mut ret = 0x0_u16;
77        $uut = $sim.watch(|x| !x.$($fifo).+.bus_read.empty.val(), $uut)?;
78        ret = $uut.$($fifo).+.bus_read.data.val().to_u16();
79        $uut.$($fifo).+.bus_read.read.next = true;
80        wait_clock_cycle!($sim, $($clock).+, $uut);
81        $uut.$($fifo).+.bus_read.read.next = false;
82        $uut = $sim.watch(|x| !x.$($fifo).+.bus_read.empty.val(), $uut)?;
83        let byte: u8 = $uut.$($fifo).+.bus_read.data.val().to_u8();
84        ret = (ret << 8) | (byte as u16);
85        $uut.$($fifo).+.bus_read.read.next = true;
86        wait_clock_cycle!($sim, $($clock).+, $uut);
87        $uut.$($fifo).+.bus_read.read.next = false;
88        ret
89    }}
90}
91
92#[macro_export]
93macro_rules! hls_host_get_words {
94    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo: ident).+, $count: expr) => {
95        {
96            let mut ret = vec![];
97            for _ in 0..$count {
98                ret.push(hls_host_get_word!($sim, $($clock).+, $uut, $($fifo).+));
99            }
100            ret
101        }
102    }
103}
104
105#[macro_export]
106macro_rules! hls_host_put_word {
107    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo:ident).*, $val: expr) => {
108        hls_fifo_write!($sim, $($clock).+, $uut, $($fifo).+.bus_write, [($val >> 8) as u8, ($val & 0xFF) as u8]);
109    }
110}
111
112#[macro_export]
113macro_rules! hls_host_ping {
114    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo:ident).+, $data: expr) => {
115        hls_host_put_word!($sim, $($clock).+, $uut, $($fifo).+, 0x0100_u16 | ($data as u16));
116    }
117}
118
119#[macro_export]
120macro_rules! hls_host_noop {
121    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo: ident).+) => {
122        hls_host_put_word!($sim, $($clock).+, $uut, $($fifo).+, 0x0000_u16);
123    }
124}
125
126#[macro_export]
127macro_rules! hls_host_write {
128    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo: ident).+, $addr: expr, $data: expr) => {
129        hls_host_put_word!($sim, $($clock).+, $uut, $($fifo).+, 0x0300_u16 | ($addr as u16));
130        hls_host_put_word!($sim, $($clock).+, $uut, $($fifo).+, $data.len() as u16);
131        for word in $data {
132            hls_host_put_word!($sim, $($clock).+, $uut, $($fifo).+, word as u16);
133        }
134    }
135}
136
137#[macro_export]
138macro_rules! hls_host_issue_read {
139    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo: ident).+, $addr: expr, $count: expr) => {
140        {
141            hls_host_put_word!($sim, $($clock).+, $uut, $($fifo).+, 0x0200_u16 | ($addr as u16));
142            hls_host_put_word!($sim, $($clock).+, $uut, $($fifo).+, $count as u16);
143        }
144    }
145}
146
147#[macro_export]
148macro_rules! hls_host_drain {
149    ($sim: ident, $($clock: ident).+, $uut: ident, $($fifo: ident).+) => {
150        {
151            $uut.$($fifo).+.bus_read.read.next = false;
152            while (!$uut.$($fifo).+.bus_read.empty.val()) {
153                $uut.$($fifo).+.bus_read.read.next = true;
154                wait_clock_cycle!($sim, $($clock).+, $uut);
155                $uut.$($fifo).+.bus_read.read.next = false;
156            }
157        }
158    }
159}
160
161#[macro_export]
162macro_rules! bus_address_strobe {
163    ($sim: ident, $uut: ident, $field: ident, $addr: expr) => {{
164        wait_clock_true!($sim, $field.clock, $uut);
165        $uut.$field.address.next = ($addr as u32).to_bits();
166        $uut.$field.address_strobe.next = true;
167        wait_clock_cycle!($sim, $field.clock, $uut);
168        $uut.$field.address_strobe.next = false;
169        $uut.$field.address.next = 0.into();
170        $uut = $sim.watch(|x| x.$field.ready.val(), $uut)?;
171    }};
172}
173
174#[macro_export]
175macro_rules! bus_write_strobe {
176    ($sim: ident,$uut: ident, $field: ident, $val: expr) => {{
177        wait_clock_true!($sim, $field.clock, $uut);
178        $uut.$field.from_controller.next = ($val).to_bits();
179        $uut.$field.strobe.next = true;
180        wait_clock_cycle!($sim, $field.clock, $uut);
181        $uut.$field.strobe.next = false;
182    }};
183}
rust_hdl_lib_hls/sim.rs

rust_hdl_lib_hls/
sim.rs
