rust_hdl_lib_hls/
miso_port.rs

1// A simple, local bus for attaching stuff together on the FPGA
2use crate::bus::SoCPortResponder;
3use rust_hdl_lib_core::prelude::*;
4use rust_hdl_lib_widgets::prelude::*;
5
6// An input port simply stores the value written to it's input back to
7// the master.  The address comparison logic is registered to improve the
8// timing analysis of the bus.
9#[derive(LogicBlock, Default)]
10pub struct MISOPort<const D: usize> {
11    pub bus: SoCPortResponder<D>,
12    pub port_in: Signal<In, Bits<D>>,
13    pub clock_out: Signal<Out, Clock>,
14    pub ready_in: Signal<In, Bit>,
15    pub strobe_out: Signal<Out, Bit>,
16    address_active: DFF<Bit>,
17}
18
19impl<const D: usize> Logic for MISOPort<D> {
20    #[hdl_gen]
21    fn update(&mut self) {
22        self.clock_out.next = self.bus.clock.val();
23        dff_setup!(self, clock_out, address_active);
24        self.address_active.d.next = self.bus.select.val();
25        self.bus.to_controller.next = 0.into();
26        self.bus.ready.next = false;
27        self.strobe_out.next = false;
28        if self.address_active.q.val() {
29            self.bus.ready.next = self.ready_in.val();
30            self.bus.to_controller.next = self.port_in.val();
31            self.strobe_out.next = self.bus.strobe.val();
32        }
33    }
34}
35
36#[test]
37fn test_local_in_port_is_synthesizable() {
38    let mut dev = MISOPort::<16>::default();
39    dev.connect_all();
40    let vlog = generate_verilog(&dev);
41    yosys_validate("localin", &vlog).unwrap();
42}
rust_hdl_lib_hls/miso_port.rs

rust_hdl_lib_hls/
miso_port.rs
