1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150

use crate::core::ast::{Verilog, VerilogExpression};
use crate::core::atom::{Atom, AtomKind};
use crate::core::block::Block;
use crate::core::check_error::{CheckError, PathedName, PathedNameList};
use crate::core::named_path::NamedPath;
use crate::core::probe::Probe;
use crate::core::verilog_visitor::VerilogVisitor;
use std::collections::HashSet;

#[derive(Copy, Clone, Debug, PartialEq)]
enum Mode {
    Ignore,
    Read,
    Write,
}

pub struct VerilogLogicLoopDetector {
    local_vars_written: HashSet<String>,
    mode: Mode,
    violations: Vec<String>,
}

impl Default for VerilogLogicLoopDetector {
    fn default() -> Self {
        Self {
            local_vars_written: Default::default(),
            mode: Mode::Ignore,
            violations: Default::default(),
        }
    }
}

impl VerilogVisitor for VerilogLogicLoopDetector {
    fn visit_slice_assignment(
        &mut self,
        base: &VerilogExpression,
        _width: &usize,
        offset: &VerilogExpression,
        replacement: &VerilogExpression,
    ) {
        let current_mode = self.mode;
        self.mode = Mode::Read;
        self.visit_expression(offset);
        self.visit_expression(replacement);
        self.mode = Mode::Write;
        self.visit_expression(base);
        self.mode = current_mode;
    }

    fn visit_signal(&mut self, c: &str) {
        let myname = c.replace("$next", "");
        match self.mode {
            Mode::Ignore => {}
            Mode::Write => {
                self.local_vars_written.insert(myname);
            }
            Mode::Read => {
                if !self.local_vars_written.contains(&myname) {
                    self.violations.push(myname);
                }
            }
        }
    }

    fn visit_assignment(&mut self, l: &VerilogExpression, r: &VerilogExpression) {
        let current_mode = self.mode;
        self.mode = Mode::Read;
        self.visit_expression(r);
        self.mode = Mode::Write;
        self.visit_expression(l);
        self.mode = current_mode;
    }
}

fn get_logic_loop_candidates(uut: &dyn Block) -> Vec<String> {
    match &uut.hdl() {
        Verilog::Combinatorial(code) => {
            let mut det = VerilogLogicLoopDetector::default();
            det.visit_block(code);
            if det.violations.is_empty() {
                vec![]
            } else {
                det.violations
            }
        }
        _ => vec![],
    }
}

#[derive(Default, Clone, Debug)]
struct LocalVars {
    path: NamedPath,
    names: Vec<HashSet<String>>,
    loops: PathedNameList,
}

impl LocalVars {
    fn update_loops(&mut self, candidates: &[String]) {
        for candidate in candidates {
            if self.names.last().unwrap().contains(candidate) {
                self.loops.push(PathedName {
                    path: self.path.to_string(),
                    name: candidate.to_string(),
                })
            }
        }
    }
}

impl Probe for LocalVars {
    fn visit_start_scope(&mut self, name: &str, _node: &dyn Block) {
        self.path.push(name);
        self.names.push(Default::default());
    }

    fn visit_start_namespace(&mut self, name: &str, _node: &dyn Block) {
        self.path.push(name);
        self.names.push(Default::default());
    }

    fn visit_atom(&mut self, name: &str, signal: &dyn Atom) {
        match signal.kind() {
            AtomKind::LocalSignal | AtomKind::OutputParameter => {
                self.names.last_mut().unwrap().insert(name.to_string());
            }
            _ => {}
        }
    }

    fn visit_end_namespace(&mut self, _name: &str, _node: &dyn Block) {
        self.names.pop();
        self.path.pop();
    }

    fn visit_end_scope(&mut self, _name: &str, node: &dyn Block) {
        self.update_loops(&get_logic_loop_candidates(node));
        self.path.pop();
        self.names.pop();
    }
}

pub fn check_logic_loops(uut: &dyn Block) -> Result<(), CheckError> {
    let mut visitor = LocalVars::default();
    uut.accept("uut", &mut visitor);
    if visitor.loops.is_empty() {
        Ok(())
    } else {
        Err(CheckError::LogicLoops(visitor.loops))
    }
}