Module rust_hdl::core

The core RustHDL module. Defines variable width bits, signals, logical blocks, etc.

Modules

ast

bits

Module that supports arbitrary width bit vectors The [Bits] type is used to capture values with arbitrarily large (but known) bit length

block

check_connected

check_error

check_logic_loops

check_timing

clock

code_writer

constant

constraint

direction

logic

module_defines

named_path

path_tools

prelude

probe

signal

signed

simulate

struct_valued

synth

timing

type_descriptor

vcd_probe

verilog_gen

verilog_visitor

yosys