1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

use crate::core::prelude::*;

// We want to be able to combine a set of signals into a struct
#[cfg(test)]
#[derive(Clone, Copy, Debug, PartialEq, Eq, LogicState)]
enum CmdType {
    Noop,
    Read,
    Write,
}

#[cfg(test)]
#[derive(Copy, Clone, Default, Debug, PartialEq, Eq, LogicStruct)]
struct MIGCmd {
    pub cmd: CmdType,
    pub active: Bit,
    pub len: Bits<6>,
}

#[test]
fn test_composite() {
    assert_eq!(MIGCmd::BITS, 9);
    let x = MIGCmd {
        cmd: CmdType::Read,
        active: true,
        len: 35.into(),
    };

    let y: Bits<9> = x.into();
    assert_eq!(y.get_bits::<{ CmdType::BITS }>(0), 1);
    assert_eq!(y.get_bits::<{ bool::BITS }>(2), true);
    assert_eq!(y.get_bits::<6>(3), 35);
    let _x = MIGCmd {
        cmd: CmdType::Write,
        active: false,
        len: 30.into(),
    };
}

#[derive(Clone, Debug, Default, Copy, PartialEq, LogicStruct)]
struct CoreConfig {
    pub foo: Bits<6>,
    pub bar: Bits<32>,
    pub baz: Bits<16>,
}

#[derive(LogicBlock)]
struct TestBlock {
    pub f: Signal<Out, Bits<6>>,
    pub g: Signal<Out, Bits<32>>,
    pub h: Signal<Out, Bits<16>>,
    vals: Constant<CoreConfig>,
}

impl Logic for TestBlock {
    #[hdl_gen]
    fn update(&mut self) {
        self.f.next = self.vals.val().foo;
        self.g.next = self.vals.val().bar;
        self.h.next = self.vals.val().baz;
    }
}

impl Default for TestBlock {
    fn default() -> Self {
        Self {
            f: Default::default(),
            g: Default::default(),
            h: Default::default(),
            vals: Constant::new(CoreConfig {
                foo: 7.into(),
                bar: 32.into(),
                baz: 8.into(),
            }),
        }
    }
}

#[test]
fn test_test_block_synthesizes() {
    let mut uut = TopWrap::new(TestBlock::default());
    uut.connect_all();
    yosys_validate("test_block", &generate_verilog(&uut)).unwrap();
}