List of all items

Structs

• bsp::alchitry_cu::ice_pll::ICE40PLLBlock
• bsp::alchitry_cu::ice_pll::ICEPLL40Core
• bsp::ok_core::clock::ClockBuffer
• bsp::ok_core::ok_download::OpalKellyDownload32FIFO
• bsp::ok_core::ok_download::OpalKellyDownloadFIFO
• bsp::ok_core::ok_hi::OpalKellyHostInterface
• bsp::ok_core::ok_host::OpalKellyHost
• bsp::ok_core::ok_pipe::BTPipeIn
• bsp::ok_core::ok_pipe::BTPipeOut
• bsp::ok_core::ok_pipe::PipeIn
• bsp::ok_core::ok_pipe::PipeOut
• bsp::ok_core::ok_trigger::TriggerIn
• bsp::ok_core::ok_trigger::TriggerOut
• bsp::ok_core::ok_wire::WireIn
• bsp::ok_core::ok_wire::WireOut
• bsp::ok_core::spi::OKSPIMaster
• bsp::ok_core::spi::OKSPIMasterAddressConfig
• bsp::ok_xem6010::OKTest1
• bsp::ok_xem6010::XEM6010
• bsp::ok_xem6010::ddr_fifo::DDRFIFO
• bsp::ok_xem6010::mcb_if::MCBInterface1GDDR2
• bsp::ok_xem6010::mig::CommandPort
• bsp::ok_xem6010::mig::MemoryInterfaceGenerator
• bsp::ok_xem6010::mig::ReadPort
• bsp::ok_xem6010::mig::WritePort
• bsp::ok_xem6010::ok_download_ddr::OpalKellyDDRBackedDownloadFIFO
• bsp::ok_xem6010::pll::PLLFreqSynthesis
• bsp::ok_xem6010::pll::Spartan6PLLSettings
• bsp::ok_xem6010::synth::ISEOptions
• bsp::ok_xem7010::XEM7010
• bsp::ok_xem7010::ddr_fifo7::DDR7FIFO
• bsp::ok_xem7010::download::OpalKellyDDRBackedDownloadFIFO7Series
• bsp::ok_xem7010::mcb_if::MCBInterface4GDDR3
• bsp::ok_xem7010::mig7::MemoryInterfaceGenerator7Series
• bsp::ok_xem7010::synth::VivadoOptions
• bsp::ok_xem7010::sys_clock::OpalKellySystemClock7
• core::ast::BlackBox
• core::ast::Wrapper
• core::bitvec::BitVec
• core::clock::Clock
• core::code_writer::CodeWriter
• core::constant::Constant
• core::constraint::FalsePathRegexp
• core::constraint::InputTimingConstraint
• core::constraint::OutputTimingConstraint
• core::constraint::PeriodicTiming
• core::constraint::PinConstraint
• core::constraint::VivadoInputTimingConstraint
• core::constraint::VivadoOutputTimingConstraint
• core::direction::In
• core::direction::InOut
• core::direction::Local
• core::direction::Out
• core::module_defines::ModuleDefines
• core::named_path::NamedPath
• core::shortbitvec::ShortBitVec
• core::signal::Signal
• core::signed::Signed
• core::simulate::Sim
• core::simulate::Simulation
• core::vcd_probe::VCDProbe
• core::verilog_gen::VerilogCodeGenerator
• core::yosys::TopWrap
• sim::ad7193_sim::AD7193Config
• sim::ad7193_sim::AD7193Simulator
• sim::ads868x_sim::ADS868XSimulator
• sim::max31856_sim::MAX31856Simulator
• sim::muxed_ad7193_sim::MuxedAD7193Simulators
• sim::muxed_ads868x_sim::MuxedADS868XSimulators
• sim::muxed_max31856_sim::MuxedMAX31856Simulators
• widgets::async_fifo::AsynchronousFIFO
• widgets::cross_fifo::CrossNarrowFIFO
• widgets::cross_fifo::CrossWidenFIFO
• widgets::dff::DFF
• widgets::edge_detector::EdgeDetector
• widgets::fifo_expander_n::FIFOExpanderN
• widgets::fifo_logic::FIFOReadLogic
• widgets::fifo_logic::FIFOWriteLogic
• widgets::fifo_reducer::FIFOReducer
• widgets::fifo_reducer_n::FIFOReducerN
• widgets::mac_fir::MultiplyAccumulateSymmetricFiniteImpulseResponseFilter
• widgets::pulser::Pulser
• widgets::pwm::PulseWidthModulator
• widgets::ram::RAM
• widgets::ram::RAMWrite
• widgets::rom::ROM
• widgets::shot::Shot
• widgets::spi_master::SPIConfig
• widgets::spi_master::SPIMaster
• widgets::spi_master::SPIWires
• widgets::spi_slave::SPISlave
• widgets::strobe::Strobe
• widgets::sync_fifo::SynchronousFIFO
• widgets::sync_rom::SyncROM
• widgets::synchronizer::BitSynchronizer
• widgets::synchronizer::SyncReceiver
• widgets::synchronizer::SyncSender
• widgets::synchronizer::VectorSynchronizer

Enums

• bsp::ok_xem6010::ddr_fifo::DDRFIFOState
• bsp::ok_xem6010::ddr_fifo::MIGInstruction
• bsp::ok_xem6010::pll::PLLSettingsValidation
• bsp::ok_xem7010::ddr_fifo7::DDR7FIFOState
• bsp::ok_xem7010::mig7::MIG7SimState
• core::ast::Verilog
• core::bits::Bits
• core::constraint::Constraint
• core::constraint::SignalType
• core::constraint::SlewType
• core::constraint::Timing
• core::constraint::TimingRelative
• core::constraint::TimingRelativeEdge
• core::simulate::SimError
• core::synth::VCDValue
• core::yosys::SynthError
• widgets::fifo_expander_n::WordOrder
• widgets::synchronizer::SyncReceiverState
• widgets::synchronizer::SyncSenderState

Traits

• bsp::ok_core::bsp::OpalKellyBSP
• core::block::Block
• core::direction::Direction
• core::logic::Logic
• core::logic::LogicLink
• core::probe::Probe
• core::synth::Synth
• core::verilog_visitor::VerilogVisitor

Macros

• declare_async_fifo
• declare_expanding_fifo
• declare_narrowing_fifo
• declare_sync_fifo
• sim_assert
• target_path
• top_wrap
• vcd_path
• wait_clock_cycle
• wait_clock_cycles
• wait_clock_false
• wait_clock_true

Attribute Macros

• core::prelude::hdl_gen

Derive Macros

• core::prelude::LogicBlock
• core::prelude::LogicInterface
• core::prelude::LogicState

Functions

• bsp::alchitry_cu::pins::clock
• bsp::alchitry_cu::pins::leds
• bsp::alchitry_cu::pins::map_alchitry_pin_to_cu_pad
• bsp::alchitry_cu::synth::generate_bitstream
• bsp::ok_core::tools::find_ok_bus_collisions
• bsp::ok_xem6010::pins::xem_6010_base_clock
• bsp::ok_xem6010::pins::xem_6010_leds
• bsp::ok_xem6010::synth::add_mig_core_xem_6010
• bsp::ok_xem6010::synth::generate_bitstream_xem_6010
• bsp::ok_xem6010::synth::synth_obj
• bsp::ok_xem7010::pins::xem_7010_leds
• bsp::ok_xem7010::pins::xem_7010_neg_clock
• bsp::ok_xem7010::pins::xem_7010_pos_clock
• bsp::ok_xem7010::synth::add_mig_core_xem_7010
• bsp::ok_xem7010::synth::generate_bitstream_xem_7010
• bsp::ok_xem7010::synth::synth_obj
• core::bits::bit_cast
• core::bits::bits
• core::bits::clog2
• core::check_connected::check_connected
• core::clock::freq_hz_to_period_femto
• core::logic::logic_connect_fn
• core::logic::logic_connect_link_fn
• core::module_defines::generate_verilog
• core::module_defines::generate_verilog_unchecked
• core::signal::get_signal_id
• core::signed::signed
• core::signed::signed_bit_cast
• core::signed::signed_cast
• core::signed::unsigned_bit_cast
• core::signed::unsigned_cast
• core::simulate::simulate
• core::struct_valued::raw_cast
• core::vcd_probe::write_vcd_change
• core::vcd_probe::write_vcd_dump
• core::vcd_probe::write_vcd_header
• core::verilog_gen::filter_blackbox_directives
• core::verilog_gen::verilog_combinatorial
• core::verilog_visitor::walk_assignment
• core::verilog_visitor::walk_binop
• core::verilog_visitor::walk_block
• core::verilog_visitor::walk_block_or_conditional
• core::verilog_visitor::walk_case
• core::verilog_visitor::walk_cast
• core::verilog_visitor::walk_conditional
• core::verilog_visitor::walk_expression
• core::verilog_visitor::walk_index
• core::verilog_visitor::walk_index_assignment
• core::verilog_visitor::walk_index_replacement
• core::verilog_visitor::walk_lhs_expression
• core::verilog_visitor::walk_loop
• core::verilog_visitor::walk_match
• core::verilog_visitor::walk_paren
• core::verilog_visitor::walk_slice
• core::verilog_visitor::walk_slice_assignment
• core::verilog_visitor::walk_statement
• core::verilog_visitor::walk_unop
• core::yosys::yosys_validate
• toolchain::icestorm::generate_pcf
• toolchain::ise::collect_xrefs
• toolchain::ise::generate_ucf
• toolchain::ise::substitute_refs
• toolchain::map_signal_type_to_xilinx_string
• toolchain::vivado::generate_xdc
• widgets::rom::make_btree_from_iterable

Typedefs

• bsp::ok_core::ok_download::OKDLFIFO
• bsp::ok_core::ok_download::OKStageFIFO
• core::bits::Bit
• core::shortbitvec::ShortType
• core::simulate::Result

Constants

• bsp::alchitry_cu::pins::CLOCK_SPEED_100MHZ
• bsp::ok_core::MHZ48
• bsp::ok_core::prelude::MHZ100
• bsp::ok_core::prelude::MHZ48
• core::clock::NANOS_PER_FEMTO
• core::shortbitvec::SHORT_BITS
• sim::ad7193_sim::AD7193_REG_WIDTHS