Struct rust_hdl_widgets::synchronizer::SyncSender

pub struct SyncSender<T: Synth> {
    pub sig_in: Signal<In, T>,
    pub clock: Signal<In, Clock>,
    pub sig_cross: Signal<Out, T>,
    pub flag_out: Signal<Out, Bit>,
    pub ack_in: Signal<In, Bit>,
    pub busy: Signal<Out, Bit>,
    pub send: Signal<In, Bit>,
    /* private fields */
}

When you need to send many bits between two clock domains, it is risky to use a vector of BitSynchronizer structs. That is because, you cannot guarantee at any given moment that all of the bits of your multi-bit signal will cross into the new clock domain at once. So to synchronize a multi-bit signal, use a SyncSender and SyncReceiver pair. These widgets will use a set of handshake signals to move a value from one clock domain to another safely. Note that while the state machine is executing, the synchronizer will indicate it is busy. Crossing clock domains with greater ease is best done with an [AsynchronousFIFO].

Fields

sig_in: Signal<In, T>

The input signal to synchronize across clock domains

clock: Signal<In, Clock>

The input signals are assumed to be synchronous to this clock

sig_cross: Signal<Out, T>

These are the wires used to send signals to the SyncReceiver.

flag_out: Signal<Out, Bit>

A protocol flag signal indicating that data is ready to be transferred to the second clock doamin.

ack_in: Signal<In, Bit>

A protocol flag signal indicating that the data has been transferred to the second clock domain.

busy: Signal<Out, Bit>

A signal indicating that the SyncSender is busy transferring data to the second clock domain.

send: Signal<In, Bit>

A protocol signal - raise this high for one cycle to latch [sig_in].

Trait Implementations

impl<T: Synth> Block for SyncSender<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Default + Synth> Default for SyncSender<T>

fn default() -> SyncSender<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for SyncSender<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>