rust_hdl_widgets/sdram/
timings.rs

1#[derive(Copy, Clone, Debug, PartialEq)]
2pub struct MemoryTimings {
3    pub initial_delay_in_nanoseconds: f64,
4    pub t_rp_recharge_period_nanoseconds: f64,
5    pub t_rfc_autorefresh_period_nanoseconds: f64,
6    pub load_mode_command_timing_clocks: u32,
7    pub t_ras_row_active_min_time_nanoseconds: f64,
8    pub t_rc_row_to_row_min_time_nanoseconds: f64,
9    pub t_rcd_row_to_column_min_time_nanoseconds: f64,
10    pub t_rrd_bank_to_bank_activate_min_time_nanoseconds: f64,
11    pub t_wr_write_recovery_time_nanoseconds: f64,
12    pub t_refresh_max_interval_nanoseconds: f64,
13    pub clock_speed_hz: f64,
14    pub columns_per_bank: u32,
15    pub rows_per_bank: u32,
16    pub num_banks: u32,
17}
18
19impl MemoryTimings {
20    pub fn mt48lc8m16a2(clock_speed_hz: f64) -> Self {
21        Self {
22            initial_delay_in_nanoseconds: 100.0e3,
23            t_rp_recharge_period_nanoseconds: 20.0,
24            t_rfc_autorefresh_period_nanoseconds: 66.0,
25            load_mode_command_timing_clocks: 2,
26            t_ras_row_active_min_time_nanoseconds: 44.0,
27            t_rc_row_to_row_min_time_nanoseconds: 66.0,
28            t_rcd_row_to_column_min_time_nanoseconds: 20.0,
29            t_rrd_bank_to_bank_activate_min_time_nanoseconds: 15.0,
30            t_wr_write_recovery_time_nanoseconds: 15.0,
31            t_refresh_max_interval_nanoseconds: 16e6 / 4096.0,
32            clock_speed_hz,
33            columns_per_bank: 512,
34            rows_per_bank: 4096,
35            num_banks: 4,
36        }
37    }
38    pub fn is42s16320f7(clock_speed_hz: f64) -> Self {
39        Self {
40            initial_delay_in_nanoseconds: 100.0e3,
41            t_rp_recharge_period_nanoseconds: 15.0,
42            t_rfc_autorefresh_period_nanoseconds: 60.0,
43            load_mode_command_timing_clocks: 2,
44            t_ras_row_active_min_time_nanoseconds: 37.0,
45            t_rc_row_to_row_min_time_nanoseconds: 60.0,
46            t_rcd_row_to_column_min_time_nanoseconds: 15.0,
47            t_rrd_bank_to_bank_activate_min_time_nanoseconds: 14.0,
48            t_wr_write_recovery_time_nanoseconds: 14.0,
49            t_refresh_max_interval_nanoseconds: 16e6 / 4096.0,
50            clock_speed_hz,
51            columns_per_bank: 1024, // 10 bits
52            rows_per_bank: 8192,    // 13 bits
53            num_banks: 4,           // 2 bits - total address is thus 25 bits.
54        }
55    }
56    pub fn fast_boot_sim(clock_speed_hz: f64) -> Self {
57        Self {
58            initial_delay_in_nanoseconds: 1000.0,
59            t_rp_recharge_period_nanoseconds: 20.0,
60            t_rfc_autorefresh_period_nanoseconds: 66.0,
61            load_mode_command_timing_clocks: 2,
62            t_ras_row_active_min_time_nanoseconds: 44.0,
63            t_rc_row_to_row_min_time_nanoseconds: 66.0,
64            t_rcd_row_to_column_min_time_nanoseconds: 20.0,
65            t_rrd_bank_to_bank_activate_min_time_nanoseconds: 15.0,
66            t_wr_write_recovery_time_nanoseconds: 14.0,
67            t_refresh_max_interval_nanoseconds: 16e6 / 8192.0,
68            clock_speed_hz,
69            columns_per_bank: 32,
70            rows_per_bank: 32,
71            num_banks: 4,
72        }
73    }
74    pub fn t_boot(&self) -> u16 {
75        nanos_to_clocks(self.initial_delay_in_nanoseconds, self.clock_speed_hz)
76    }
77    pub fn t_rp(&self) -> u16 {
78        nanos_to_clocks(self.t_rp_recharge_period_nanoseconds, self.clock_speed_hz)
79    }
80    pub fn t_rfc(&self) -> u16 {
81        nanos_to_clocks(
82            self.t_rfc_autorefresh_period_nanoseconds,
83            self.clock_speed_hz,
84        )
85    }
86    pub fn t_ras(&self) -> u16 {
87        nanos_to_clocks(
88            self.t_ras_row_active_min_time_nanoseconds,
89            self.clock_speed_hz,
90        )
91    }
92    pub fn t_rc(&self) -> u16 {
93        nanos_to_clocks(
94            self.t_rc_row_to_row_min_time_nanoseconds,
95            self.clock_speed_hz,
96        )
97    }
98    pub fn t_rcd(&self) -> u16 {
99        nanos_to_clocks(
100            self.t_rcd_row_to_column_min_time_nanoseconds,
101            self.clock_speed_hz,
102        )
103    }
104    pub fn t_rrd(&self) -> u16 {
105        nanos_to_clocks(
106            self.t_rrd_bank_to_bank_activate_min_time_nanoseconds,
107            self.clock_speed_hz,
108        )
109    }
110    pub fn t_wr(&self) -> u16 {
111        nanos_to_clocks(
112            self.t_wr_write_recovery_time_nanoseconds,
113            self.clock_speed_hz,
114        )
115    }
116    pub fn t_refresh_max(&self) -> u16 {
117        nanos_to_clocks(self.t_refresh_max_interval_nanoseconds, self.clock_speed_hz)
118    }
119}
120
121pub fn nanos_to_clocks(time_in_nanos: f64, clock_speed_hz: f64) -> u16 {
122    let clock_period_in_nanos = 1.0e9 / clock_speed_hz;
123    (time_in_nanos / clock_period_in_nanos).ceil() as u16
124}
rust_hdl_widgets/sdram/timings.rs

rust_hdl_widgets/sdram/
timings.rs
