rust_hdl_widgets/
edge_detector.rs

1use rust_hdl_core::prelude::*;
2
3use crate::{dff::DFF, dff_setup};
4
5#[derive(LogicBlock)]
6pub struct EdgeDetector {
7    pub input_signal: Signal<In, Bit>,
8    pub edge_signal: Signal<Out, Bit>,
9    pub clock: Signal<In, Clock>,
10    prev: DFF<Bit>,
11    current: DFF<Bit>,
12    is_rising: Constant<Bit>,
13}
14
15impl EdgeDetector {
16    pub fn new(is_rising: bool) -> Self {
17        Self {
18            input_signal: Default::default(),
19            edge_signal: Default::default(),
20            clock: Default::default(),
21            prev: Default::default(),
22            current: Default::default(),
23            is_rising: Constant::new(is_rising),
24        }
25    }
26}
27
28impl Logic for EdgeDetector {
29    #[hdl_gen]
30    fn update(&mut self) {
31        dff_setup!(self, clock, prev, current);
32        self.prev.d.next = self.current.q.val();
33        self.current.d.next = self.is_rising.val() ^ self.input_signal.val();
34        self.edge_signal.next = !self.current.q.val() & self.prev.q.val();
35    }
36}
37
38#[test]
39fn test_edge_detector_synthesizes() {
40    let mut uut = EdgeDetector::new(false);
41    uut.connect_all();
42    yosys_validate("edge", &generate_verilog(&uut)).unwrap();
43}
rust_hdl_widgets/edge_detector.rs

rust_hdl_widgets/
edge_detector.rs
