rust_hdl_widgets/
dff.rs

1use rust_hdl_core::prelude::*;
2
3#[derive(Clone, Debug, LogicBlock)]
4pub struct DFF<T: Synth> {
5    pub d: Signal<In, T>,
6    pub q: Signal<Out, T>,
7    pub clock: Signal<In, Clock>,
8}
9
10impl<T: Synth> Default for DFF<T> {
11    fn default() -> DFF<T> {
12        Self {
13            d: Signal::default(),
14            q: Signal::default(),
15            clock: Signal::default(),
16        }
17    }
18}
19
20impl<T: Synth> Logic for DFF<T> {
21    fn update(&mut self) {
22        if self.clock.pos_edge() {
23            self.q.next = self.d.val()
24        }
25    }
26    fn connect(&mut self) {
27        self.q.connect();
28    }
29    fn hdl(&self) -> Verilog {
30        Verilog::Custom(format!(
31            "\
32initial begin
33   q = {:x};
34end
35
36always @(posedge clock) begin
37   q <= d;
38end
39      ",
40            T::default().verilog()
41        ))
42    }
43    fn timing(&self) -> Vec<TimingInfo> {
44        vec![TimingInfo {
45            name: "dff".into(),
46            clock: "clock".into(),
47            inputs: vec!["d".into()],
48            outputs: vec!["q".into()],
49        }]
50    }
51}
52
53#[macro_export]
54macro_rules! dff_setup {
55    ($self: ident, $clock: ident, $($dff: ident),+) => {
56        $($self.$dff.clock.next = $self.$clock.val());+;
57        $($self.$dff.d.next = $self.$dff.q.val());+;
58    }
59}
rust_hdl_widgets/dff.rs

rust_hdl_widgets/
dff.rs
