rust_hdl_widgets/
edge_ff.rs

1use rust_hdl_core::prelude::*;
2use rust_hdl_core::timing::TimingInfo;
3
4#[derive(Clone, Debug, LogicBlock, Default)]
5pub struct EdgeDFF<T: Synth> {
6    pub d: Signal<In, T>,
7    pub q: Signal<Out, T>,
8    pub clk: Signal<In, Clock>,
9}
10
11impl<T: Synth> EdgeDFF<T> {
12    pub fn new(init: T) -> EdgeDFF<T> {
13        Self {
14            d: Signal::default(),
15            q: Signal::new_with_default(init),
16            clk: Signal::default(),
17        }
18    }
19}
20
21// TODO - make this specializable
22impl<T: Synth> Logic for EdgeDFF<T> {
23    fn update(&mut self) {
24        if self.clk.pos_edge() {
25            self.q.next = self.d.val()
26        }
27    }
28    fn connect(&mut self) {
29        self.q.connect();
30    }
31    fn hdl(&self) -> Verilog {
32        Verilog::Custom(format!(
33            "\
34initial begin
35   q = {:x};
36end
37
38always @(posedge clk) q <= d;",
39            self.q.verilog()
40        ))
41    }
42    fn timing(&self) -> Vec<TimingInfo> {
43        vec![TimingInfo {
44            name: "edge_ff".to_string(),
45            clock: "clk".to_string(),
46            inputs: vec!["d".into()],
47            outputs: vec!["q".into()],
48        }]
49    }
50}
rust_hdl_widgets/edge_ff.rs

rust_hdl_widgets/
edge_ff.rs
