rust_hdl_widgets/fifo/
fifo_register.rs

1use rust_hdl_core::prelude::*;
2
3use crate::{dff::DFF, dff_setup};
4
5// A synchronous FIFO of depth 1, backed by a pair of registers
6#[derive(LogicBlock, Default)]
7pub struct RegisterFIFO<T: Synth> {
8    pub data_in: Signal<In, T>,
9    pub data_out: Signal<Out, T>,
10    pub write: Signal<In, Bit>,
11    pub read: Signal<In, Bit>,
12    pub full: Signal<Out, Bit>,
13    pub empty: Signal<Out, Bit>,
14    pub clock: Signal<In, Clock>,
15    value: DFF<T>,
16    filled: DFF<Bit>,
17    error: DFF<Bit>,
18}
19
20impl<T: Synth> Logic for RegisterFIFO<T> {
21    #[hdl_gen]
22    fn update(&mut self) {
23        dff_setup!(self, clock, value, filled, error);
24        // There are two states to consider.  The first is the
25        // empty state (no internal data)
26        if self.write.val() {
27            self.value.d.next = self.data_in.val();
28        }
29        self.data_out.next = self.value.q.val();
30        self.full.next = self.filled.q.val() & !self.read.val();
31        self.empty.next = !self.filled.q.val();
32        if !self.filled.q.val() {
33            // We are empty.  This means our empty flag is true, and
34            // should be no read.
35            if self.write.val() {
36                self.value.d.next = self.data_in.val();
37                self.filled.d.next = true;
38            }
39            // If we have a read with no data, this is an error condition !
40            if self.read.val() {
41                self.error.d.next = true;
42            }
43        } else {
44            // We have data.  It is possible we can get both a
45            // read and a write (pipeline)
46            // If we have a write with no read, this is an error condition!
47            if self.write.val() & !self.read.val() {
48                self.error.d.next = true;
49            }
50            // If we have a read with no write, then we will be empty next cycle
51            if self.read.val() & !self.write.val() {
52                self.filled.d.next = false;
53            }
54        }
55    }
56}
57
58#[test]
59fn test_register_fifo_is_synthesizable() {
60    let mut uut = RegisterFIFO::<Bits<16>>::default();
61    uut.connect_all();
62    let vlog = generate_verilog(&uut);
63    yosys_validate("fifo_reg", &vlog).unwrap();
64}
rust_hdl_widgets/fifo/fifo_register.rs

rust_hdl_widgets/fifo/
fifo_register.rs
