rust_hdl_widgets/sdram/
mod.rs

1pub mod basic_controller;
2pub mod buffer;
3pub mod burst_controller;
4pub mod cmd;
5pub mod fifo_sdram;
6pub mod timings;
7
8use rust_hdl_core::prelude::*;
9
10#[derive(Clone, Copy, Debug, PartialEq)]
11pub enum OutputBuffer {
12    Wired,
13    DelayOne,
14    DelayTwo,
15}
16
17#[derive(LogicInterface, Clone, Debug, Default)]
18#[join = "SDRAMDevice"]
19pub struct SDRAMDriver<const D: usize> {
20    pub clk: Signal<Out, Clock>,
21    pub we_not: Signal<Out, Bit>,
22    pub cas_not: Signal<Out, Bit>,
23    pub ras_not: Signal<Out, Bit>,
24    pub cs_not: Signal<Out, Bit>,
25    pub bank: Signal<Out, Bits<2>>,
26    pub address: Signal<Out, Bits<13>>,
27    pub write_data: Signal<Out, Bits<D>>,
28    pub read_data: Signal<In, Bits<D>>,
29    pub write_enable: Signal<Out, Bit>,
30}
31
32#[derive(LogicInterface, Clone, Debug, Default)]
33#[join = "SDRAMDriver"]
34pub struct SDRAMDevice<const D: usize> {
35    pub clk: Signal<In, Clock>,
36    pub we_not: Signal<In, Bit>,
37    pub cas_not: Signal<In, Bit>,
38    pub ras_not: Signal<In, Bit>,
39    pub cs_not: Signal<In, Bit>,
40    pub bank: Signal<In, Bits<2>>,
41    pub address: Signal<In, Bits<13>>,
42    pub write_data: Signal<In, Bits<D>>,
43    pub read_data: Signal<Out, Bits<D>>,
44    pub write_enable: Signal<In, Bit>,
45}
rust_hdl_widgets/sdram/mod.rs

rust_hdl_widgets/sdram/
mod.rs
