rust_hdl_widgets/
delay_line.rs

1use crate::{dff::DFF, dff_setup};
2use array_init::array_init;
3use rust_hdl_core::prelude::*;
4
5// A configurable delay line.  Given writes at the input,
6// will write those values back to the output N cycles later,
7// where N is an input of max bit width W.
8#[derive(LogicBlock)]
9pub struct DelayLine<D: Synth, const N: usize, const W: usize> {
10    pub clock: Signal<In, Clock>,
11    pub data_in: Signal<In, D>,
12    pub data_out: Signal<Out, D>,
13    pub delay: Signal<In, Bits<W>>,
14    line: [DFF<D>; N],
15}
16
17impl<D: Synth, const N: usize, const W: usize> Default for DelayLine<D, N, W> {
18    fn default() -> Self {
19        assert!(W >= clog2(N));
20        Self {
21            clock: Default::default(),
22            data_in: Default::default(),
23            data_out: Default::default(),
24            delay: Default::default(),
25            line: array_init(|_| Default::default()),
26        }
27    }
28}
29
30impl<D: Synth, const N: usize, const W: usize> Logic for DelayLine<D, N, W> {
31    #[hdl_gen]
32    fn update(&mut self) {
33        // Clock all of the delay lines
34        for i in 0..N {
35            self.line[i].clock.next = self.clock.val();
36        }
37        for i in 1..N {
38            self.line[i].d.next = self.line[i - 1].q.val();
39        }
40        // Connect the head to the input signal
41        self.line[0].d.next = self.data_in.val();
42        // Connect the delay line to the appropriate output
43        self.data_out.next = self.data_in.val();
44        for i in 0..N {
45            if self.delay.val().index() == i + 1 {
46                self.data_out.next = self.line[i].q.val();
47            }
48        }
49    }
50}
51
52#[cfg(test)]
53type DelayLineTest = DelayLine<Bits<8>, 8, 3>;
54
55#[test]
56fn test_delay_synthesizes() {
57    let mut uut = DelayLineTest::default();
58    uut.connect_all();
59    let vlog = generate_verilog(&uut);
60    yosys_validate("delay_line", &vlog).unwrap();
61}
62
63#[test]
64fn test_delay_operation() {
65    let mut uut = DelayLineTest::default();
66    uut.connect_all();
67    let mut sim = Simulation::new();
68    sim.add_clock(5, |x: &mut Box<DelayLineTest>| {
69        x.clock.next = !x.clock.val();
70    });
71    sim.add_testbench(move |mut sim: Sim<DelayLineTest>| {
72        let mut x = sim.init()?;
73        wait_clock_true!(sim, clock, x);
74        x.delay.next = 0.into();
75        x.data_in.next = 0xDE.into();
76        wait_clock_false!(sim, clock, x);
77        sim_assert!(sim, x.data_out.val() == 0xDE, x);
78        wait_clock_true!(sim, clock, x);
79        x.data_in.next = 0.into();
80        wait_clock_false!(sim, clock, x);
81        sim_assert!(sim, x.data_out.val() == 0x0, x);
82        wait_clock_true!(sim, clock, x);
83        for delay in 1..7 {
84            wait_clock_cycles!(sim, clock, x, 4);
85            x.delay.next = delay.into();
86            x.data_in.next = (0xDE + delay).into();
87            wait_clock_cycle!(sim, clock, x);
88            x.data_in.next = 0x00.into();
89            wait_clock_cycles!(sim, clock, x, delay - 1);
90            sim_assert!(sim, x.data_out.val() == (0xDE + delay), x);
91        }
92        sim.done(x)
93    });
94    sim.run(Box::new(uut), 2_000).unwrap();
95}
rust_hdl_widgets/delay_line.rs

rust_hdl_widgets/
delay_line.rs
