rust_hdl_sim/
muxed_ads868x_sim.rs

1use super::ads868x_sim::ADS868XSimulator;
2use rust_hdl_core::prelude::*;
3use rust_hdl_widgets::prelude::*;
4
5#[derive(LogicBlock)]
6pub struct MuxedADS868XSimulators<const N: usize> {
7    // Input SPI bus
8    pub wires: SPIWiresSlave,
9    pub addr: Signal<In, Bits<3>>,
10    pub mux: MuxSlaves<N, 3>,
11    pub clock: Signal<In, Clock>,
12    adcs: [ADS868XSimulator; N],
13}
14
15impl<const N: usize> MuxedADS868XSimulators<N> {
16    pub fn new(config: SPIConfig) -> Self {
17        assert!(N <= 8);
18        Self {
19            wires: Default::default(),
20            mux: Default::default(),
21            addr: Default::default(),
22            clock: Default::default(),
23            adcs: array_init::array_init(|_| ADS868XSimulator::new(config)),
24        }
25    }
26}
27
28impl<const N: usize> Logic for MuxedADS868XSimulators<N> {
29    #[hdl_gen]
30    fn update(&mut self) {
31        SPIWiresSlave::link(&mut self.wires, &mut self.mux.from_master);
32        for i in 0..N {
33            self.adcs[i].clock.next = self.clock.val();
34            SPIWiresMaster::join(&mut self.mux.to_slaves[i], &mut self.adcs[i].wires);
35        }
36        self.mux.sel.next = self.addr.val();
37    }
38}
39
40#[test]
41fn test_mux_is_synthesizable() {
42    let mut uut: MuxedADS868XSimulators<8> =
43        MuxedADS868XSimulators::new(ADS868XSimulator::spi_hw());
44    uut.connect_all();
45    yosys_validate("mux_8689", &generate_verilog(&uut)).unwrap();
46}
rust_hdl_sim/muxed_ads868x_sim.rs

rust_hdl_sim/
muxed_ads868x_sim.rs
