rust_hdl_sim/
muxed_ad7193_sim.rs

1use super::ad7193_sim::{AD7193Config, AD7193Simulator};
2use rust_hdl_core::prelude::*;
3use rust_hdl_widgets::prelude::*;
4
5#[derive(LogicBlock)]
6pub struct MuxedAD7193Simulators {
7    // Input SPI bus
8    pub wires: SPIWiresSlave,
9    pub addr: Signal<In, Bits<3>>,
10    pub mux: MuxSlaves<8, 3>,
11    pub clock: Signal<In, Clock>,
12    adcs: [AD7193Simulator; 8],
13}
14
15impl MuxedAD7193Simulators {
16    pub fn new(config: AD7193Config) -> Self {
17        Self {
18            wires: Default::default(),
19            mux: Default::default(),
20            addr: Default::default(),
21            clock: Default::default(),
22            adcs: array_init::array_init(|_| AD7193Simulator::new(config)),
23        }
24    }
25}
26
27impl Logic for MuxedAD7193Simulators {
28    #[hdl_gen]
29    fn update(&mut self) {
30        SPIWiresSlave::link(&mut self.wires, &mut self.mux.from_master);
31        for i in 0..8 {
32            self.adcs[i].clock.next = self.clock.val();
33            SPIWiresMaster::join(&mut self.mux.to_slaves[i], &mut self.adcs[i].wires);
34        }
35        self.mux.sel.next = self.addr.val();
36    }
37}
38
39#[test]
40fn test_mux_is_synthesizable() {
41    let mut uut = MuxedAD7193Simulators::new(AD7193Config::hw());
42    uut.connect_all();
43    yosys_validate("mux_7193", &generate_verilog(&uut)).unwrap();
44}
rust_hdl_sim/muxed_ad7193_sim.rs

rust_hdl_sim/
muxed_ad7193_sim.rs
