rust_hdl_sim/
muxed_max31856_sim.rs

1use super::max31856_sim::MAX31856Simulator;
2use rust_hdl_core::prelude::*;
3use rust_hdl_widgets::prelude::*;
4
5#[derive(LogicBlock)]
6pub struct MuxedMAX31856Simulators {
7    // Input SPI bus
8    pub wires: SPIWiresSlave,
9    pub mux: MuxSlaves<8, 3>,
10    pub addr: Signal<In, Bits<3>>,
11    pub clock: Signal<In, Clock>,
12    adcs: Vec<MAX31856Simulator>,
13}
14
15impl MuxedMAX31856Simulators {
16    pub fn new(config: SPIConfig) -> Self {
17        Self {
18            wires: Default::default(),
19            mux: Default::default(),
20            addr: Default::default(),
21            clock: Default::default(),
22            adcs: (0..8).map(|_| MAX31856Simulator::new(config)).collect(),
23        }
24    }
25}
26
27impl Logic for MuxedMAX31856Simulators {
28    #[hdl_gen]
29    fn update(&mut self) {
30        SPIWiresSlave::link(&mut self.wires, &mut self.mux.from_master);
31        self.mux.sel.next = self.addr.val();
32        for i in 0..8 {
33            self.adcs[i].clock.next = self.clock.val();
34            SPIWiresMaster::join(&mut self.mux.to_slaves[i], &mut self.adcs[i].wires);
35        }
36    }
37}
38
39#[test]
40fn test_mux_is_synthesizable() {
41    use super::ad7193_sim::AD7193Config;
42    let mut uut = MuxedMAX31856Simulators::new(AD7193Config::hw().spi);
43    uut.connect_all();
44    yosys_validate("mux_31865", &generate_verilog(&uut)).unwrap();
45}
rust_hdl_sim/muxed_max31856_sim.rs

rust_hdl_sim/
muxed_max31856_sim.rs
