rust_hdl_hls/
sdram_fifo.rs

1use crate::bus::{FIFOReadResponder, FIFOWriteResponder};
2use rust_hdl_core::prelude::*;
3use rust_hdl_widgets::prelude::*;
4
5#[derive(LogicBlock)]
6pub struct SDRAMFIFO<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> {
7    pub clock: Signal<In, Clock>,
8    pub sdram: SDRAMDriver<D>,
9    pub ram_clock: Signal<In, Clock>,
10    pub bus_write: FIFOWriteResponder<Bits<D>>,
11    pub bus_read: FIFOReadResponder<Bits<D>>,
12    controller: SDRAMFIFOController<R, C, P, D, A>,
13}
14
15impl<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> Logic
16    for SDRAMFIFO<R, C, P, D, A>
17{
18    #[hdl_gen]
19    fn update(&mut self) {
20        self.controller.data_in.next = self.bus_write.data.val();
21        self.controller.write.next = self.bus_write.write.val();
22        self.bus_write.full.next = self.controller.full.val();
23        self.bus_write.almost_full.next = self.controller.full.val();
24        self.bus_read.data.next = self.controller.data_out.val();
25        self.bus_read.empty.next = self.controller.empty.val();
26        self.bus_read.almost_empty.next = self.controller.empty.val();
27        self.controller.read.next = self.bus_read.read.val();
28        clock!(self, clock, controller);
29        self.controller.ram_clock.next = self.ram_clock.val();
30        SDRAMDriver::<D>::link(&mut self.sdram, &mut self.controller.sdram);
31    }
32}
33
34impl<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize>
35    SDRAMFIFO<R, C, P, D, A>
36{
37    pub fn new(
38        cas_delay: u32,
39        timings: MemoryTimings,
40        buffer: OutputBuffer,
41    ) -> SDRAMFIFO<R, C, P, D, A> {
42        Self {
43            clock: Default::default(),
44            sdram: Default::default(),
45            ram_clock: Default::default(),
46            bus_write: Default::default(),
47            bus_read: Default::default(),
48            controller: SDRAMFIFOController::new(cas_delay, timings, buffer),
49        }
50    }
51}
52
53#[test]
54fn test_sdram_fifo_synthesizes() {
55    let mut uut = SDRAMFIFO::<6, 4, 4, 16, 12>::new(
56        3,
57        MemoryTimings::fast_boot_sim(125e6),
58        OutputBuffer::Wired,
59    );
60    uut.connect_all();
61    let vlog = generate_verilog(&uut);
62    yosys_validate("sdram_fifo_hls", &vlog).unwrap();
63}
rust_hdl_hls/sdram_fifo.rs

rust_hdl_hls/
sdram_fifo.rs
