rust_hdl_hls/
reducer.rs

1use crate::bus::{FIFOReadController, FIFOWriteController};
2use rust_hdl_core::prelude::*;
3use rust_hdl_widgets::prelude::{FIFOReducerN, WordOrder};
4
5#[derive(LogicBlock)]
6pub struct Reducer<const DW: usize, const DN: usize> {
7    pub bus_read: FIFOReadController<Bits<DW>>,
8    pub bus_write: FIFOWriteController<Bits<DN>>,
9    pub clock: Signal<In, Clock>,
10    reducer: FIFOReducerN<DW, DN>,
11}
12
13impl<const DW: usize, const DN: usize> Logic for Reducer<DW, DN> {
14    #[hdl_gen]
15    fn update(&mut self) {
16        // Connect the clock
17        clock!(self, clock, reducer);
18        // Connect the HLS read bus to the native signals
19        self.bus_read.read.next = self.reducer.read.val();
20        self.reducer.empty.next = self.bus_read.empty.val();
21        self.reducer.data_in.next = self.bus_read.data.val();
22        // Connect the HDL write bus to the native signals
23        self.reducer.full.next = self.bus_write.full.val();
24        self.bus_write.data.next = self.reducer.data_out.val();
25        self.bus_write.write.next = self.reducer.write.val();
26    }
27}
28
29impl<const DW: usize, const DN: usize> Reducer<DW, DN> {
30    pub fn new(order: WordOrder) -> Self {
31        Self {
32            bus_read: Default::default(),
33            bus_write: Default::default(),
34            clock: Default::default(),
35            reducer: FIFOReducerN::new(order),
36        }
37    }
38}
rust_hdl_hls/reducer.rs

rust_hdl_hls/
reducer.rs
