rust_hdl_hls/
miso_fifo_port.rs

1use crate::bus::{FIFOWriteResponder, SoCPortResponder};
2use crate::fifo::SyncFIFO;
3use crate::miso_port::MISOPort;
4use rust_hdl_core::prelude::*;
5
6#[derive(LogicBlock, Default)]
7pub struct MISOFIFOPort<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> {
8    pub bus: SoCPortResponder<W>,
9    port: MISOPort<W>,
10    fifo: SyncFIFO<Bits<W>, N, NP1, BLOCK>,
11    pub fifo_bus: FIFOWriteResponder<Bits<W>>,
12}
13
14impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Logic
15    for MISOFIFOPort<W, N, NP1, BLOCK>
16{
17    #[hdl_gen]
18    fn update(&mut self) {
19        SoCPortResponder::<W>::link(&mut self.bus, &mut self.port.bus);
20        self.fifo.clock.next = self.bus.clock.val();
21        self.fifo.bus_read.read.next = self.port.strobe_out.val();
22        self.port.ready_in.next = !self.fifo.bus_read.empty.val();
23        self.port.port_in.next = self.fifo.bus_read.data.val();
24        FIFOWriteResponder::<Bits<W>>::link(&mut self.fifo_bus, &mut self.fifo.bus_write);
25    }
26}
27
28#[test]
29fn test_miso_fifo_port_is_synthesizable() {
30    let mut dev = MISOFIFOPort::<16, 4, 5, 1>::default();
31    dev.bus.link_connect_dest();
32    dev.fifo_bus.link_connect_dest();
33    dev.connect_all();
34    let vlog = generate_verilog(&dev);
35    yosys_validate("miso_fifo_port", &vlog).unwrap();
36}
rust_hdl_hls/miso_fifo_port.rs

rust_hdl_hls/
miso_fifo_port.rs
