rust_hdl_hls/
fifo_linker.rs

1use crate::bus::{FIFOReadController, FIFOWriteController};
2use rust_hdl_core::prelude::*;
3
4#[derive(LogicBlock, Default)]
5pub struct FIFOLink<T: Synth> {
6    pub read: FIFOReadController<T>,
7    pub write: FIFOWriteController<T>,
8    will_transfer: Signal<Local, Bit>,
9}
10
11impl<T: Synth> Logic for FIFOLink<T> {
12    #[hdl_gen]
13    fn update(&mut self) {
14        self.will_transfer.next = !self.read.empty.val() & !self.write.full.val();
15        self.write.data.next = self.read.data.val();
16        self.read.read.next = self.will_transfer.val();
17        self.write.write.next = self.will_transfer.val();
18    }
19}
20
21#[test]
22fn test_link_synthesizes() {
23    let mut uut: FIFOLink<Bits<8>> = Default::default();
24    uut.connect_all();
25    yosys_validate("fifo_link", &generate_verilog(&uut)).unwrap();
26}
rust_hdl_hls/fifo_linker.rs

rust_hdl_hls/
fifo_linker.rs
