rust_hdl_fpga_support/lattice/ecp5/
oddr.rs

1use rust_hdl_core::prelude::*;
2
3#[derive(Clone, Debug, LogicBlock, Default)]
4pub struct OutputDDR {
5    pub d: Signal<In, Bits<2>>,
6    pub clock: Signal<In, Clock>,
7    pub q: Signal<Out, Bit>,
8    pub reset: Signal<In, Bit>,
9    _capture: Bits<2>,
10}
11
12impl Logic for OutputDDR {
13    fn update(&mut self) {
14        if self.clock.pos_edge() {
15            self._capture = self.d.val();
16            self.q.next = self._capture.get_bit(0);
17        }
18        if self.clock.neg_edge() {
19            self.q.next = self._capture.get_bit(1);
20        }
21        if self.reset.val().into() {
22            self._capture = 0.into();
23            self.q.next = false;
24        }
25    }
26    fn connect(&mut self) {
27        self.q.connect();
28    }
29    fn hdl(&self) -> Verilog {
30        Verilog::Wrapper(Wrapper {
31            code: r##"
32ODDRX1F inst_ODDRX1F(.SCLK(clock), .RST(reset), .D0(d[0]), .D1(d[1]), .Q(q));
33            "##
34            .into(),
35            cores: r##"
36(* blackbox *)
37module ODDRX1F(input D0, input D1, input SCLK, input RST, output Q);
38endmodule
39            "##
40            .into(),
41        })
42    }
43}
44
45#[test]
46fn test_oddr_synthesizes() {
47    let mut uut = OutputDDR::default();
48    uut.connect_all();
49    yosys_validate("oddr", &generate_verilog(&uut)).unwrap();
50}
rust_hdl_fpga_support/lattice/ecp5/oddr.rs

rust_hdl_fpga_support/lattice/ecp5/
oddr.rs
