rust_hdl_fpga_support/lattice/ecp5/
edge_flip_flop.rs

1use rust_hdl_core::prelude::*;
2
3#[derive(Clone, Debug, LogicBlock, Default)]
4pub struct EdgeFlipFlop<T: Synth> {
5    pub d: Signal<In, T>,
6    pub q: Signal<Out, T>,
7    pub clock: Signal<In, Clock>,
8}
9
10fn wrapper_once() -> &'static str {
11    r##"
12OFS1P3DX inst_OFS1P3DX(.SCLK(clock), .SP(1'b1), .D(d), .Q(q), .CD(1'b0));
13    "##
14}
15
16fn wrapper_multiple(count: usize) -> String {
17    (0..count)
18        .map(|x| {
19            format!(
20                "
21OFS1P3DX ofs_{x}(.SCLK(clock), .SP(1'b1), .D(d[{x}]), .Q(q[{x}]), .CD(1'b0));
22",
23                x = x
24            )
25        })
26        .collect::<Vec<_>>()
27        .join("\n")
28}
29
30impl<T: Synth> Logic for EdgeFlipFlop<T> {
31    fn update(&mut self) {
32        if self.clock.pos_edge() {
33            self.q.next = self.d.val()
34        }
35    }
36    fn connect(&mut self) {
37        self.q.connect();
38    }
39    fn hdl(&self) -> Verilog {
40        Verilog::Wrapper(Wrapper {
41            code: if T::BITS == 1 {
42                wrapper_once().to_string()
43            } else {
44                wrapper_multiple(T::BITS)
45            },
46            cores: r##"
47(* blackbox *)
48module OFS1P3DX(input D, input SP, input SCLK, input CD, output Q);
49endmodule
50            "##
51            .into(),
52        })
53    }
54}
55
56#[test]
57fn test_eflop_synthesizes() {
58    let mut uut = EdgeFlipFlop::<Bits<8>>::default();
59    uut.connect_all();
60    yosys_validate("eflop", &generate_verilog(&uut)).unwrap();
61}
rust_hdl_fpga_support/lattice/ecp5/edge_flip_flop.rs

rust_hdl_fpga_support/lattice/ecp5/
edge_flip_flop.rs
