rust_hdl_fpga_support/lattice/ecp5/
output_buffer.rs

1use rust_hdl_core::prelude::*;
2
3#[derive(Clone, Debug, LogicBlock, Default)]
4pub struct OutputBuffer {
5    pub i: Signal<In, Bit>,
6    pub o: Signal<Out, Bit>,
7}
8
9impl Logic for OutputBuffer {
10    fn update(&mut self) {
11        self.o.next = self.i.val();
12    }
13    fn connect(&mut self) {
14        self.o.connect();
15    }
16    fn hdl(&self) -> Verilog {
17        Verilog::Wrapper(Wrapper {
18            code: r##"
19OB inst_OB(.I(i), .O(o));
20            "##
21            .into(),
22            cores: r##"
23(* blackbox *)
24module OB(input I, output O);
25endmodule
26            "##
27            .into(),
28        })
29    }
30}
31
32#[test]
33fn test_output_buffer_synthesizes() {
34    let mut uut = OutputBuffer::default();
35    uut.connect_all();
36    yosys_validate("obuf", &generate_verilog(&uut)).unwrap();
37}