rust_hdl_fpga_support/toolchains/
mod.rs

1use rust_hdl_core::prelude::*;
2
3pub fn map_signal_type_to_lattice_string(k: &SignalType) -> &str {
4    match k {
5        SignalType::LowVoltageCMOS_3v3 => "LVCMOS33",
6        _ => panic!(
7            "Unsupported mapping for signal type {:?} in Lattice mapping",
8            k
9        ),
10    }
11}
12
13pub fn map_signal_type_to_xilinx_string(k: &SignalType) -> &str {
14    match k {
15        SignalType::LowVoltageCMOS_1v8 => "LVCMOS18",
16        SignalType::LowVoltageCMOS_3v3 => "LVCMOS33",
17        SignalType::StubSeriesTerminatedLogic_II => "SSTL18_II",
18        SignalType::DifferentialStubSeriesTerminatedLogic_II => "DIFF_SSTL18_II",
19        SignalType::StubSeriesTerminatedLogic_II_No_Termination => "SSTL18_II | IN_TERM=NONE",
20        SignalType::DifferentialStubSeriesTerminatedLogic_II_No_Termination => {
21            "DIFF_SSTL18_II | IN_TERM=NONE"
22        }
23        SignalType::Custom(c) => c,
24        SignalType::LowVoltageDifferentialSignal_2v5 => "LVDS_25",
25        SignalType::StubSeriesTerminatedLogic_1v5 => "SSTL15",
26        SignalType::LowVoltageCMOS_1v5 => "LVCMOS15",
27        SignalType::DifferentialStubSeriesTerminatedLogic_1v5 => "DIFF_SSTL15",
28    }
29}
30
31pub mod ecp5;
32pub mod icestorm;
33pub mod ise;
34pub mod vivado;