rust_hdl_core/
constraint.rs

1#![allow(non_camel_case_types)]
2
3#[derive(Clone, Debug)]
4pub enum SignalType {
5    LowVoltageCMOS_1v8,
6    LowVoltageCMOS_3v3,
7    StubSeriesTerminatedLogic_II,
8    DifferentialStubSeriesTerminatedLogic_II,
9    StubSeriesTerminatedLogic_II_No_Termination,
10    DifferentialStubSeriesTerminatedLogic_II_No_Termination,
11    LowVoltageDifferentialSignal_2v5,
12    StubSeriesTerminatedLogic_1v5,
13    LowVoltageCMOS_1v5,
14    DifferentialStubSeriesTerminatedLogic_1v5,
15    Custom(String),
16}
17
18#[derive(Clone, Debug)]
19pub struct PeriodicTiming {
20    pub net: String,
21    pub period_nanoseconds: f64,
22    pub duty_cycle: f64,
23}
24
25#[derive(Clone, Copy, Debug)]
26pub enum TimingRelative {
27    Before,
28    After,
29}
30
31impl ToString for TimingRelative {
32    fn to_string(&self) -> String {
33        match self {
34            TimingRelative::Before => "BEFORE",
35            TimingRelative::After => "AFTER",
36        }
37        .into()
38    }
39}
40
41#[derive(Clone, Debug)]
42pub struct FalsePathRegexp {
43    pub from_regexp: String,
44    pub to_regexp: String,
45}
46
47#[derive(Clone, Copy, Debug)]
48pub enum TimingRelativeEdge {
49    Rising,
50    Falling,
51}
52
53impl ToString for TimingRelativeEdge {
54    fn to_string(&self) -> String {
55        match self {
56            TimingRelativeEdge::Falling => "FALLING",
57            TimingRelativeEdge::Rising => "RISING",
58        }
59        .into()
60    }
61}
62
63#[derive(Clone, Debug)]
64pub struct VivadoInputTimingConstraint {
65    pub min_nanoseconds: f64,
66    pub max_nanoseconds: f64,
67    pub multicycle: usize,
68    pub clock: String,
69}
70
71#[derive(Clone, Debug)]
72pub struct VivadoOutputTimingConstraint {
73    pub delay_nanoseconds: f64,
74    pub clock: String,
75}
76
77#[derive(Clone, Copy, Debug)]
78pub struct InputTimingConstraint {
79    pub offset_nanoseconds: f64,
80    pub valid_duration_nanoseconds: f64,
81    pub relative: TimingRelative,
82    pub edge_sense: TimingRelativeEdge,
83    pub to_signal_id: usize,
84    pub to_signal_bit: Option<usize>,
85}
86
87#[derive(Clone, Copy, Debug)]
88pub struct OutputTimingConstraint {
89    pub offset_nanoseconds: f64,
90    pub relative: TimingRelative,
91    pub edge_sense: TimingRelativeEdge,
92    pub to_signal_id: usize,
93    pub to_signal_bit: Option<usize>,
94}
95
96#[derive(Clone, Debug)]
97pub enum Timing {
98    Periodic(PeriodicTiming),
99    InputTiming(InputTimingConstraint),
100    OutputTiming(OutputTimingConstraint),
101    VivadoInputTiming(VivadoInputTimingConstraint),
102    VivadoOutputTiming(VivadoOutputTimingConstraint),
103    VivadoClockGroup(Vec<Vec<String>>),
104    VivadoFalsePath(FalsePathRegexp),
105    Custom(String),
106}
107
108#[derive(Clone, Debug)]
109pub enum Constraint {
110    Location(String),
111    Kind(SignalType),
112    Timing(Timing),
113    Custom(String),
114    Slew(SlewType),
115}
116
117#[derive(Clone, Debug)]
118pub enum SlewType {
119    Normal,
120    Fast,
121}
122
123#[derive(Clone, Debug)]
124pub struct PinConstraint {
125    pub index: usize,
126    pub constraint: Constraint,
127}
rust_hdl_core/constraint.rs

rust_hdl_core/
constraint.rs
