rust-hdl-core-0.46.0
- rust-hdl-core 0.46.0
- Docs.rs crate page
- MIT
- Links
- Homepage
- Repository
- crates.io
- Source
- Owners
- samitbasu
- Dependencies
- anyhow ^1 normal
  
  array-init ^2.0.0 normal
  
  crossbeam ^0.8.1 normal
  
  embed-doc-image ^0.1.4 normal
  
  evalexpr ^6.3.0 normal
  
  num-bigint ^0.4.0 normal
  
  num-traits ^0.2.14 normal
  
  petgraph ^0.6.0 normal
  
  rand ^0.8 normal
  
  regex ^1.5.4 normal
  
  rust-hdl-macros ^0.46.0 normal
  
  seq-macro ^0.3.1 normal
  
  substring ^1 normal
  
  svg ^0.10.0 normal
  
  vcd ^0.6.1 normal
- Versions
- 21.21% of the crate is documented
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docs.rs
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Rust

Module constraint

rust_hdl_core0.46.0

Module constraint

Module Items

Structs
Enums

In crate rust_hdl_core

Modules

ast
bits
block
check_connected
check_error
check_logic_loops
check_timing
check_write_inputs
clock
code_writer
constant
constraint
direction
logic
module_defines
named_path
path_tools
prelude
probe
signal
signed
simulate
synth
timing
top_wrap
type_descriptor
vcd_probe
verilog_gen
verilog_visitor
yosys

Macros

clock
sim_assert
sim_assert_eq
simple_sim
target_path
vcd_path
wait_clock_cycle
wait_clock_cycles
wait_clock_false
wait_clock_true

Module constraint

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Structs§

FalsePathRegexp
InputTimingConstraint
OutputTimingConstraint
PeriodicTiming
PinConstraint
VivadoInputTimingConstraint
VivadoOutputTimingConstraint

Enums§

Constraint
SignalType
SlewType
Timing
TimingRelative
TimingRelativeEdge