Crate rust_hdl_core

Modules

• ast
• bits
  Module that supports arbitrary width bit vectors The [Bits] type is used to capture values with arbitrarily large (but known) bit length
• block
• check_connected
• check_error
• check_logic_loops
• check_timing
• check_write_inputs
• clock
• code_writer
• constant
• constraint
• direction
• logic
• module_defines
• named_path
• path_tools
• prelude
• probe
• signal
• signed
• simulate
• synth
• timing
• top_wrap
• type_descriptor
• vcd_probe
• verilog_gen
• verilog_visitor
• yosys

Macros

• clock
  The clock! macro is used to connect a set of devices to a common clock. The macro takes a variable number of arguments:
• sim_assert
• sim_assert_eq
• simple_sim
• target_path
• vcd_path
• wait_clock_cycle
• wait_clock_cycles
• wait_clock_false
• wait_clock_true