List of all items

Structs

• ast::BlackBox
• ast::VerilogCase
• ast::VerilogConditional
• ast::VerilogIndexAssignment
• ast::VerilogLinkDetails
• ast::VerilogLiteral
• ast::VerilogLoop
• ast::VerilogMatch
• ast::Wrapper
• bitvec::BitVec
• clock::Clock
• code_writer::CodeWriter
• constant::Constant
• constraint::FalsePathRegexp
• constraint::InputTimingConstraint
• constraint::OutputTimingConstraint
• constraint::PeriodicTiming
• constraint::PinConstraint
• constraint::VivadoInputTimingConstraint
• constraint::VivadoOutputTimingConstraint
• direction::In
• direction::InOut
• direction::Local
• direction::Out
• module_defines::ModuleDefines
• named_path::NamedPath
• shortbitvec::ShortBitVec
• signal::Signal
• simulate::Sim
• simulate::Simulation
• vcd_probe::VCDProbe
• verilog_gen::VerilogCodeGenerator

Enums

• ast::Verilog
• ast::VerilogBlockOrConditional
• ast::VerilogExpression
• ast::VerilogLink
• ast::VerilogOp
• ast::VerilogOpUnary
• ast::VerilogStatement
• atom::AtomKind
• bits::Bits
• constraint::Constraint
• constraint::SignalType
• constraint::SlewType
• constraint::Timing
• constraint::TimingRelative
• constraint::TimingRelativeEdge
• simulate::SimError
• synth::VCDValue

Traits

• atom::Atom
• block::Block
• direction::Direction
• logic::Logic
• logic::LogicLink
• probe::Probe
• synth::Synth
• verilog_visitor::VerilogVisitor

Macros

• sim_assert
• wait_clock_cycle
• wait_clock_cycles
• wait_clock_false
• wait_clock_true

Attribute Macros

• prelude::hdl_gen

Derive Macros

• prelude::LogicBlock
• prelude::LogicInterface
• prelude::LogicState

Functions

• bits::bit_cast
• bits::bits
• bits::clog2
• check_connected::check_connected
• clock::freq_hz_to_period_femto
• logic::logic_connect_fn
• logic::logic_connect_link_fn
• module_defines::generate_verilog
• module_defines::generate_verilog_unchecked
• signal::get_signal_id
• simulate::simulate
• struct_valued::raw_cast
• vcd_probe::write_vcd_change
• vcd_probe::write_vcd_dump
• vcd_probe::write_vcd_header
• verilog_gen::filter_blackbox_directives
• verilog_gen::verilog_combinatorial
• verilog_visitor::walk_assignment
• verilog_visitor::walk_binop
• verilog_visitor::walk_block
• verilog_visitor::walk_block_or_conditional
• verilog_visitor::walk_case
• verilog_visitor::walk_cast
• verilog_visitor::walk_conditional
• verilog_visitor::walk_expression
• verilog_visitor::walk_index
• verilog_visitor::walk_index_assignment
• verilog_visitor::walk_index_replacement
• verilog_visitor::walk_lhs_expression
• verilog_visitor::walk_loop
• verilog_visitor::walk_match
• verilog_visitor::walk_paren
• verilog_visitor::walk_slice
• verilog_visitor::walk_slice_assignment
• verilog_visitor::walk_statement
• verilog_visitor::walk_unop

Typedefs

• ast::VerilogBlock
• bits::Bit
• shortbitvec::ShortType
• simulate::Result

Constants

• clock::NANOS_PER_FEMTO
• shortbitvec::SHORT_BITS