1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73

use std::fmt::Debug;

use crate::ast::VerilogLiteral;
use crate::bits::{Bit, Bits};
use crate::clock::Clock;

#[derive(Clone, PartialEq, Debug)]
pub enum VCDValue {
    Single(vcd::Value),
    Vector(Vec<vcd::Value>),
    String(String),
}

impl From<bool> for VCDValue {
    fn from(x: bool) -> Self {
        if x {
            VCDValue::Single(vcd::Value::V1)
        } else {
            VCDValue::Single(vcd::Value::V0)
        }
    }
}

pub trait Synth: Default + Copy + PartialEq + Debug {
    const BITS: usize;
    const ENUM_TYPE: bool = false;
    const TYPE_NAME: &'static str = "Bits";
    fn name(_ndx: usize) -> &'static str {
        ""
    }
    fn vcd(self) -> VCDValue;
    fn verilog(self) -> VerilogLiteral;
}

impl<const N: usize> Synth for Bits<N> {
    const BITS: usize = N;

    fn vcd(self) -> VCDValue {
        self.into()
    }

    fn verilog(self) -> VerilogLiteral {
        self.into()
    }
}

impl Synth for Bit {
    const BITS: usize = 1;

    fn vcd(self) -> VCDValue {
        if self {
            VCDValue::Single(vcd::Value::V1)
        } else {
            VCDValue::Single(vcd::Value::V0)
        }
    }

    fn verilog(self) -> VerilogLiteral {
        self.into()
    }
}

impl Synth for Clock {
    const BITS: usize = 1;

    fn vcd(self) -> VCDValue {
        self.0.into()
    }

    fn verilog(self) -> VerilogLiteral {
        self.0.into()
    }
}